Shared Memory Access Control for Multi-Processor Terminals
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Solution Overview
Problem
Conventional portable terminals with multiple processors face inefficiencies due to the need for separate memories and increased size, leading to bottlenecks in data communication and processing efficiency as they become more multifunctional.
Innovation Solution
A digital processing device with a shared memory system that allows multiple processors to access a common storage area, minimizing access time and optimizing operation speed by using access information to control access and partition the memory into dedicated and common sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processor is coupled to an independent memory, then each processor can access memory without interference, but the device size and complexity increase
Solution Approach 1:
Multiple processors share a common memory resource through a unified memory architecture, eliminating the need for separate memory modules for each processor. This merging approach reduces device complexity and size while maintaining reliable memory access through controlled shared access mechanisms.
Solution Approach 2:
The shared memory is divided into multiple access ports, each dedicated to a specific processor. This segmentation allows simultaneous independent access by different processors without interference, resolving the contradiction between shared memory benefits and access reliability.
2Device complexity
If multiple processors share a common memory, then device size is reduced, but access time and data transmission time increase
Solution Approach 1:
The shared memory is divided into multiple access ports, with each port dedicated to a specific processor. This allows simultaneous independent access by different processors, eliminating access time delays and enabling parallel operations without waiting for memory access completion.
Solution Approach 2:
The memory access architecture transitions from a single-bus serial access model to a multi-port parallel access model. By adding the dimension of multiple simultaneous access paths, the system achieves both shared memory benefits and reduced access time through parallelization.
3Quantity of substance
If a single memory is shared by multiple processors, then the number of memory components is reduced, but data transmission efficiency decreases
Solution Approach 1:
The memory system is segmented into multiple independent access ports, each capable of simultaneous data transmission to different processors. This segmentation maintains a single memory component while enabling parallel data transmission operations, thereby preserving productivity.
Solution Approach 2:
Each access port serves multiple functions: it provides dedicated data transmission paths for specific processors while maintaining unified memory management. This multi-functionality allows efficient data transmission across multiple processors without requiring separate memory components for each.
Data Source
AI summary
A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor is accessing a common section. With the present invention, each processor can efficiently use or/and control a shared memory by using access information.