Shared Memory Address Translation for Multi-Core Microcontrollers
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Solution Overview
Problem
In microcontrollers with multiple processing cores, duplicated code and data across applications lead to inefficient use of limited memory, as each core stores identical shared resources multiple times.
Innovation Solution
A method is implemented to analyze applications and identify common shared code and data segments, creating new binaries that separate unique and shared content, allowing shared resources to be stored once and accessed by multiple cores through address translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processing core stores its own copy of shared code and data, then each core can access its required resources independently, but memory usage increases due to duplication
Solution Approach 1:
The patent merges shared code and data segments into a common memory region that is accessible by multiple processing cores. Instead of duplicating shared resources in each core's private memory space, the system consolidates them into a single shared region, reducing overall memory consumption while maintaining accessibility for all cores that need these resources.
Solution Approach 2:
The shared memory region serves multiple functions and multiple processing cores simultaneously. A single copy of shared code or data in the shared region can be accessed by any number of cores, making the memory resource universal rather than dedicated to a single core. This multi-functionality resolves the contradiction by allowing independent access while eliminating duplication.
2Quantity of substance
If shared code and data are stored in a common memory region, then memory usage decreases by eliminating duplication, but address management becomes more complex
Solution Approach 1:
The patent segments the memory space into distinct regions: private memory regions for each processing core and a shared memory region for common resources. This segmentation provides clear boundaries and organization, making address management more systematic. Each core has well-defined access rules for different regions, which simplifies the overall address management despite the presence of shared resources.
Solution Approach 2:
The patent introduces address translation units as intermediary components that manage the mapping between virtual addresses used by processing cores and physical addresses in memory. These translation units handle the complexity of shared memory access transparently, allowing cores to use simple address generation while the intermediary manages the actual memory location resolution, thus reducing the perceived complexity for each core.
Data Source
AI summary
In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.