Shared Memory Array Drivers for Lower Die Size and Power
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Solution Overview
Problem
Existing memory devices face challenges in optimizing the placement of circuitry within memory arrays, leading to inefficiencies in die size and power consumption due to the need for multiple control signal drivers at the edges, which compromises spacing and increases production costs.
Innovation Solution
Implementing a memory array architecture where control signal drivers are shared across adjacent memory sections, reducing the need for duplicate drivers at the edges and optimizing space utilization by borrowing circuitry between neighboring tiles and sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple control signal drivers are placed at the edges of memory sections, then each memory section can be independently controlled, but the die size increases and spacing is compromised
Solution Approach 1:
The patent merges the control signal driver functionality across adjacent memory sections by sharing common drivers. Instead of having separate drivers at the edges of each section, the invention implements a shared driver architecture where a single driver serves multiple sections, thereby reducing the overall die size while maintaining reliable control signal delivery.
Solution Approach 2:
The control signal drivers are designed with multi-functionality to serve multiple memory sections. The drivers are positioned and configured to provide control signals to multiple sections simultaneously, making them universal components that reduce the total number of drivers needed and consequently reduce die size.
2Reliability
If multiple control signal drivers are placed at the edges of memory sections, then each memory section can be independently controlled, but power consumption increases
Solution Approach 1:
By merging the driver functionality across sections, the patent reduces the total number of active driver components. Fewer drivers mean less cumulative power consumption while maintaining the ability to independently control each memory section through the shared driver architecture.
Solution Approach 2:
The multi-functional drivers serve multiple sections with a single power supply, reducing the overall power consumption compared to having separate dedicated drivers for each section. The universal drivers are powered once and serve multiple purposes, thereby reducing total energy usage.
3Reliability
If multiple control signal drivers are placed at the edges of memory sections, then each memory section can be independently controlled, but production costs increase
Solution Approach 1:
The patent reduces production costs by merging driver components across sections. Fewer discrete driver components mean reduced manufacturing complexity, lower material costs, and simplified assembly processes while maintaining reliable control signal delivery to all memory sections.
Solution Approach 2:
The universal drivers reduce the bill of materials and manufacturing steps required. By using fewer standardized multi-functional driver components rather than multiple specialized single-section drivers, the invention lowers production costs while ensuring reliable control across all sections.
4Reliability
If circuitry is duplicated at the edges of memory sections, then each section has dedicated resources, but space utilization decreases
Solution Approach 1:
The patent merges duplicated circuitry into shared resources. Instead of having complete duplicate driver circuits at each section edge, the invention implements shared driver circuits that serve multiple sections, thereby improving space utilization while maintaining section control capabilities.
Solution Approach 2:
The universal drivers provide dedicated control resources to each section through their multi-functional design. These drivers can be configured to serve different sections as needed, providing dedicated control where required while sharing resources elsewhere to improve overall space utilization.
Data Source
AI summary
Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.