Shared Memory Bank Partitioning for Multi-Processor Access
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Solution Overview
Problem
In digital processing devices, the increasing multifunctionality of portable terminals leads to a bottleneck in data communication between processors, resulting in inefficient operation and reduced performance due to the need for multiple processors and memories, which increases the external size of the device and slows down processing efficiency.
Innovation Solution
A digital processing device with a shared memory system that partitions its storage area into dedicated and common sections, allowing multiple processors to access a common section simultaneously, thereby minimizing data transmission time and optimizing processor operation by providing access status information to manage data access efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple independent processors with separate memories are used to handle multifunctionality, then processing capability is improved, but device size increases and data communication efficiency deteriorates
Solution Approach 1:
The patent merges multiple independent memory systems into a single shared memory device that is accessible by multiple processors. This consolidation reduces the overall memory capacity required in the system and decreases device size while maintaining the ability to support multifunctional processing operations.
Solution Approach 2:
The shared memory device is designed to serve multiple processors simultaneously, providing a universal storage resource that can be accessed by different processing units. This multi-functional approach allows the same memory infrastructure to support various processing tasks without requiring dedicated memory for each processor.
2Productivity
If multiple independent processors with separate memories are used, then processing capability is improved, but data communication efficiency deteriorates
Solution Approach 1:
The shared memory acts as an intermediary structure that enables direct data exchange between multiple processors without requiring complex inter-processor communication protocols. By providing a common addressable space, the shared memory mediates data transfer operations and reduces communication overhead.
3Volume of stationary object
If a shared memory is introduced to reduce device size, then device complexity increases due to access management
Solution Approach 1:
The shared memory device segments its storage space into multiple banks, with each bank independently accessible by processors. This segmentation allows parallel access operations and simplifies access management by dividing the memory into smaller, independently controllable units that can be accessed simultaneously without conflict.
4Speed
If processors access shared memory simultaneously, then data transfer speed is improved, but access control complexity increases
Solution Approach 1:
By dividing the shared memory into multiple banks, the system enables simultaneous access operations where different processors can access different banks at the same time. This segmentation reduces access control complexity by allowing parallel operations without requiring complex arbitration mechanisms.
Solution Approach 2:
The system allows partial parallelism where processors can access different portions of the shared memory simultaneously. While not all accesses can be fully parallel, this partial action approach achieves sufficient speed improvement while keeping access control complexity manageable.
Data Source
AI summary
A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The shared memory is coupled to each processor though a separate bus, its storage area includes m common sections, and generates and outputs access status information related to whether an arbitrary processor is accessing at least one of the common sections. With the present invention, a control sequence of each processor can be simplified at a maximum by allowing the shared memory to generate and output access status information related to the common sections.