Shared Memory Bank Segmentation for Parallel Access Conflict Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing shared memory systems in multithreaded processor systems face significant latency and overhead due to off-chip memory location and the need for serial access to prevent conflicts, which hinders parallel processing efficiency.
Innovation Solution
A shared memory system with multiple independently-addressable banks allows parallel access to multiple locations, using address conflict logic to serialize requests as needed to avoid conflicts, and enables data broadcasting to reduce serialization requirements, facilitating low-latency access within a multithreaded processor core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If shared memory is located off-chip to provide larger storage capacity, then storage capacity is improved, but access speed deteriorates due to increased latency
Solution Approach 1:
The shared memory is divided into multiple independently-addressable banks, allowing parallel access to different segments of memory simultaneously. This segmentation enables the system to maintain large total storage capacity while providing multiple high-speed access paths, effectively resolving the contradiction between storage capacity and access speed.
2Reliability
If semaphores are used to prevent conflicting access requests, then data consistency is improved, but access efficiency deteriorates because only one thread can access shared memory at a time
Solution Approach 1:
By dividing shared memory into multiple banks that can be accessed in parallel, the system eliminates the need for semaphore-based serialization. Multiple threads can simultaneously access different banks without conflicts, maintaining data consistency through independent bank access while dramatically improving access efficiency.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory into banks that can be accessed simultaneously. This dimensional change from sequential single-bank access to parallel multi-bank access resolves the contradiction between reliability and productivity.
3Productivity
If multiple threads access the same memory location in parallel, then parallel processing throughput is improved, but access conflicts increase
Solution Approach 1:
The memory is segmented into multiple banks, allowing threads that would otherwise conflict on the same memory location to access different banks in parallel. This segmentation eliminates access conflicts while maintaining high parallel processing throughput.
4Speed
If caches are maintained for each processor to enable fast access, then access speed is improved, but system complexity increases due to cache coherence management overhead
Solution Approach 1:
The patent extracts the coherence management problem by using independently-addressable memory banks that eliminate the need for cache coherence protocols. Each bank can be accessed independently without requiring coordination between processors, reducing system complexity while maintaining fast access speeds.
Data Source
AI summary
Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.