Shared Memory Processor Circuit with Buffer Management
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Solution Overview
Problem
Harvard architecture processor circuits have a large surface area due to separate memory units for data and instructions, lack flexibility, and waste time when reading successive data items due to inefficient memory access.
Innovation Solution
A processor circuit with a shared memory unit that includes management means with buffer memory and an address comparator to optimize data reading, reducing the need for physical alterations and saving space by combining data and instructions in a single memory unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate memory units are used for data and instructions (Harvard architecture), then processing speed is improved by allowing simultaneous access, but surface area increases due to physically distinct memory units
Solution Approach 1:
The patent combines separate data memory and instruction memory into a single shared memory unit, eliminating the need for two distinct memory blocks and their separate access circuits. This merging reduces the overall surface area while maintaining the ability to achieve fast access through alternative means (buffer memory and address management).
2Speed
If separate memory units are used for data and instructions, then architecture is optimized for speed, but flexibility is reduced as physical alteration is required to adjust memory sizes
Solution Approach 1:
The patent introduces dynamic address management where a single memory unit can be flexibly allocated between data and instruction storage through software-controlled address mapping. The buffer memory and address comparator enable dynamic access patterns that can adapt to different application requirements without physical reconfiguration, making the system dynamically adaptable rather than statically fixed.
3Adaptability or versatility
If data is stored in instruction memory sections, then some flexibility is achieved, but time is wasted when reading successive data items due to reading entire memory sections
Solution Approach 1:
The patent segments the memory access process by introducing a buffer memory that holds individual data items separately from the main shared memory. The address comparator detects when successive data items are located within the same memory section, allowing the system to retrieve only the needed data from the buffer rather than reading entire memory sections, thus eliminating the time waste while preserving flexibility.
Solution Approach 2:
The buffer memory pre-loads and stores data items that are likely to be accessed sequentially. By anticipating successive data access patterns and having data ready in the buffer before it is needed, the system eliminates waiting time for memory access while maintaining the flexible storage architecture.
4Area of stationary object
If a shared memory unit is used to reduce surface area, then space is saved, but access time increases when reading successive data items without buffer optimization
Solution Approach 1:
The patent introduces buffer memory as an intermediary between the shared memory and the processing unit. This buffer acts as a temporary storage that holds data items ready for quick access, mediating between the slower shared memory and the fast processing unit. The address comparator serves as another intermediary that intelligently determines when to use the buffer, thus reducing access time while maintaining the space-efficient shared memory architecture.
Data Source
AI summary
The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.