Shared Memory Buffer Segmentation for Variable Cell Latency
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Solution Overview
Problem
Existing shared memory buffers struggle with processing variable-sized cells efficiently, leading to high administrative overhead and inadequate handling of such cells in high-throughput network switch applications and parallel computing systems.
Innovation Solution
A shared memory buffer module with a lead memory bank and a write multiplexing module that distributes leading segments to the lead memory bank and trailing segments to mutually exclusive memory banks, allowing for parallel processing and reassembly of variable-sized cells with minimal latency and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If known shared memory buffers use a cut-through approach to transmit head end of cells before tail end is completely received, then latency is reduced, but administrative overhead increases and variable-sized cells cannot be processed efficiently
Solution Approach 1:
The cell is segmented into a head end (leading segment) and a tail end (trailing segment). The head end is transmitted first through the cut-through path to reduce latency, while the trailing segment is handled separately through store-and-forward mechanism. This segmentation allows the system to benefit from both low-latency cut-through transmission and simplified error handling of fixed-size segments.
2Ease of manufacture
If known shared memory buffers are configured to process cells with fixed bit-wise widths, then processing is simplified, but variable-sized cells cannot be processed in a desirable fashion
Solution Approach 1:
Variable-sized cells are segmented into fixed-size leading and trailing segments. The leading segment contains the head end and is transmitted first, while the trailing segment contains the remaining data. This allows the buffer to maintain fixed-width processing simplicity while accommodating variable-sized cells through the segmentation approach.
Solution Approach 2:
The buffer dynamically determines the size of the leading segment based on the variable cell size, while the trailing segment maintains a fixed width. This dynamic allocation allows the system to adapt to different cell sizes while keeping the processing logic relatively simple through the use of fixed-size trailing segments.
Data Source
Figure 1A~1B
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AI summary
In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variable-sized cells. The write multiplexing module further configured to send each segment from the set of segments identified as a trailing segment to a portion of the shared memory mutually exclusive from the lead memory bank.