Shared Memory Buffer for SSD Write Operations
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Solution Overview
Problem
Current solid state drive (SSD) systems using Host Memory Buffer (HMB) incur overhead due to 'two transfers' over PCIe during write and read operations, which affects performance, endurance, and power consumption.
Innovation Solution
Implementing a shared memory buffer (SMB) with a cache structure to select and manage free write buffers, allowing direct access and internal data transfer within the SMB for write and read operations, reducing the need for PCIe transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If HMB is used for storing write buffers in SSD, then cost and power requirement are reduced, but PCIe transfer overhead increases due to two transfers
Solution Approach 1:
The shared memory buffer is segmented into multiple write buffers (first write buffer, second write buffer, etc.), each capable of independently storing write data. This segmentation allows the host to distribute write operations across multiple buffers, enabling parallel processing and reducing the frequency of PCIe transfers between host and SSD.
Solution Approach 2:
The patent combines the host memory buffer functionality with the SSD's internal memory structure by creating a shared memory buffer that resides in the host's HMB but is managed jointly by both host and SSD. This merging eliminates the need for separate buffer allocations and reduces PCIe transfer overhead through direct access mechanisms.
2Ease of manufacture
If HMB is used for storing write buffers, then DRAM cost is reduced, but write performance deteriorates due to repeated PCIe transfers
Solution Approach 1:
The host and SSD establish a shared memory buffer structure in advance during initialization, where the SSD is provided with information about the HMB's location and capacity. Write buffers are pre-allocated within this shared memory space, eliminating the need for repeated buffer allocation and data transfer operations during normal write operations.
Solution Approach 2:
The shared memory buffer acts as an intermediary structure between the host's HMB and the SSD's NAND memory. It provides a buffer zone where data can be staged for writing to NAND, reducing the frequency and impact of PCIe transfers while maintaining write performance.
3Device complexity
If traditional HMB buffer management is used, then system complexity is reduced, but data transfer efficiency decreases due to two PCIe transfers
Solution Approach 1:
The buffer management system dynamically tracks the status of each write buffer (available, locked, in-use, free) and adapts to varying write workloads. The SSD controller can lock buffers when writing data, manage buffer allocation based on current operations, and efficiently coordinate with the host's HMB, optimizing data transfer efficiency while maintaining manageable complexity through structured status tracking.
Data Source
AI summary
A method for performing a write operation includes selecting, by a host, at least a free write buffer from a plurality of write buffers of a shared memory buffer (SMB) by accessing a cache structure within the SMB for tracking the free write buffer; sending, by the host, at least a logical address accessed from the cache structure with respect to the selected write buffer to issue a write-command to a non-volatile memory; receiving a locking instruction of the selected write buffer from the non-volatile memory; updating a status of the selected write buffer within the cache structure based on the received locking instruction; and allowing the non-volatile memory to extract contents of one or more locked write buffers including the selected write buffer.