Shared Memory Buffering for Lock-Free Inter-Core Communication
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Solution Overview
Problem
Existing inter-core communication methods in multi-core microcomputers for vehicle control face delays due to simultaneous access conflicts and the need for spinlock algorithms, which cause processing delays and inefficient memory usage.
Innovation Solution
Implementing a shared memory system with buffer units and counter values to manage data access, allowing parallel processing without locking, thus avoiding data conflicts and reducing memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spinlock algorithm is used to avoid data conflict in shared memory access, then data reliability is improved, but processing speed deteriorates due to loop waiting
Solution Approach 1:
The shared memory is segmented into multiple buffer units (first buffer unit, second buffer unit, etc.), each capable of independent access. This segmentation allows different cores to access different buffer units simultaneously without conflict, eliminating the need for spinlock waiting while maintaining data reliability.
Solution Approach 2:
Buffer units serve as intermediaries between multiple cores and the shared memory. Each buffer unit acts as an independent access point that mediates data transfer between cores, allowing parallel access without direct conflict on the same memory location.
2Reliability
If spinlock algorithm is used to prohibit simultaneous access, then data conflict is avoided, but access time increases due to waiting in loop
Solution Approach 1:
By dividing the shared memory into multiple buffer units, the system enables simultaneous access from multiple cores to different units. This eliminates the need for sequential access control and loop waiting, reducing access time while maintaining data consistency through the counter value mechanism.
Solution Approach 2:
The counter value is preliminarily set to indicate the oldest data in each buffer unit. This preliminary marking allows cores to quickly identify and access valid data without waiting for lock acquisition, reducing access time while ensuring data consistency.
3Reliability
If separate buffer units are provided for each communication system, then communication reliability is improved, but memory usage increases
Solution Approach 1:
Each buffer unit is designed to be universal and can serve multiple communication systems. The buffer units are not dedicated to specific communication systems but can be dynamically allocated and shared across different communication needs, reducing total memory usage while maintaining communication reliability.
Solution Approach 2:
The system dynamically changes the state parameters of buffer units (such as the counter value indicating oldest data) to manage access across different communication systems. This parameter-based management allows the same buffer units to serve multiple communication purposes without requiring separate dedicated memory for each system.
Data Source
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AI summary
The invention provides a technology for suppressing a delay in communication between a plurality of cores that perform parallel processing. In the invention, an ECU 302 of a vehicle control system 2 includes a plurality of cores 401 and a shared memory 405. When transmitting data in the inter-core communication, a transmission side core 401-1 writes a counter value updated according to the data and a writing order to a buffer unit 901 which is determined by a counter value managed for each communication system, which is stored in each of the plurality of buffer units 901 provided in the shared memory 405. When receiving data in the inter-core communication, a reception side core 401-2 reads data from the buffer unit 901 in which the latest data for each communication system is stored, which is determined by the counter value stored in each of the plurality of buffer units 901.