Shared Memory Bus Controller for Flash and RAM
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Solution Overview
Problem
In semiconductor memory systems, the combination of flash memory and low-power RAM requires separate external memory buses for each, leading to increased size and pin count on printed circuit boards due to the need for dedicated access from a host processor, which hinders miniaturization efforts in mobile applications.
Innovation Solution
A memory system with a shared interface where a memory controller alternately couples to both a RAM and a flash memory device via a single external memory bus, utilizing multiplexing to eliminate the need for separate buses and reduce pin usage by sharing control pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate external memory buses are used for flash memory and low-power RAM, then each memory device can be accessed independently and efficiently, but the pin count and physical space on the printed circuit board increase
Solution Approach 1:
The patent combines separate memory buses for flash memory and low-power RAM into a single shared external memory bus. The memory controller is configured to selectively couple to either the flash memory device or the low-power RAM device through this shared bus, allowing both memory types to be accessed independently while using common communication pathways, thereby reducing PCB space and pin count.
Solution Approach 2:
The external memory bus is designed with universal functionality to support both flash memory and low-power RAM devices. The memory controller implements multi-functional capability to manage different memory types through the same bus interface, enabling a single bus structure to perform multiple memory access functions that previously required separate dedicated buses.
2Ease of operation
If separate external memory buses are used for flash memory and low-power RAM, then dedicated access to each memory type is ensured, but the pin count on the printed circuit board increases
Solution Approach 1:
The patent merges the separate bus interfaces into a shared external memory bus that both flash memory and low-power RAM devices connect to. The memory controller selectively couples to the appropriate memory device through this shared bus, eliminating the need for separate dedicated bus connections and thereby reducing the total pin count on the printed circuit board while preserving independent access capability.
Solution Approach 2:
The shared external memory bus is designed with universal interface capabilities that support both flash memory and low-power RAM protocols. The memory controller implements versatile access methods that can communicate with different memory types through the same physical interface, reducing pin requirements while maintaining dedicated access functionality for each memory device.
3Area of stationary object
If a shared external memory bus is used for both flash memory and low-power RAM, then pin count and physical space are reduced, but access to both memory types must be alternated
Solution Approach 1:
The memory controller implements dynamic coupling capability that allows it to selectively and rapidly switch between coupling to the flash memory device and the low-power RAM device through the shared external memory bus. This dynamic reconfiguration enables efficient time-division multiplexing of the bus resource, minimizing switching overhead and allowing rapid alternation between memory types based on access requirements.
Solution Approach 2:
The system employs periodic time-division multiplexing where the memory controller alternates between accessing flash memory and low-power RAM through the shared bus in a structured sequence. This periodic access pattern allows the bus to be efficiently shared between both memory types with predictable timing, reducing the impact of switching delays on overall system performance.
Data Source
AI summary
A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the memory controller to the first memory device and to couple the memory controller to the second memory.