Shared Memory Bus Segmentation for Multi-Type Timing
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Solution Overview
Problem
Computing systems with shared memory buses face efficiency and reliability issues due to conflicts arising from differing timing constraints of various memory types, leading to corrupted data and delayed transmissions.
Innovation Solution
Implementing adaptive operating modes such as performance and efficiency modes, where the system selectively adjusts memory bus communication based on target latency and power consumption, using distinct communication time periods and clock frequencies to segregate memory type-specific timing constraints and prevent conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared memory bus is used to communicate with multiple memory types, then device complexity is reduced, but conflicts arise due to differing timing constraints leading to data corruption and transmission delays
Solution Approach 1:
The shared memory bus communication cycle is segmented into multiple distinct time periods, with each time period dedicated to communicating with a specific memory type. This segmentation allows each memory type to operate according to its own timing constraints without interference from other memory types, eliminating conflicts while maintaining a single shared bus architecture.
2Productivity
If memory bus communication operates at high speed to reduce latency, then productivity improves, but conflicts between different memory type timing constraints increase
Solution Approach 1:
The memory bus operates in periodic cycles, with each cycle divided into distinct time periods assigned to different memory types. This periodic structure allows the system to maintain high overall bandwidth while ensuring that each memory type receives dedicated communication windows that respect its specific timing requirements, preventing conflicts even at high speeds.
3Reliability
If separate memory buses are implemented for each memory type to eliminate conflicts, then reliability improves, but device complexity and power consumption increase
Solution Approach 1:
Instead of separating memory buses in the spatial dimension (multiple physical buses), the invention separates communication in the temporal dimension by allocating different time periods to different memory types on a single shared bus. This dimensional transformation maintains physical simplicity while achieving the reliability benefits of separate buses.
4Productivity
If the system operates in performance mode with higher clock frequencies, then productivity increases, but power consumption increases
Solution Approach 1:
The system implements dynamic operating modes that allow it to adapt between performance mode (higher clock frequencies for maximum throughput) and efficiency mode (lower clock frequencies for reduced power consumption). The ability to dynamically adjust operational parameters enables the system to optimize the trade-off between productivity and power consumption based on workload requirements.
Data Source
AI summary
Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.