Shared Memory Cache Migration for Lower Invalidation Read Latency
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Solution Overview
Problem
In hierarchical memory systems, invalidating a cache line from a shared memory device leads to excessive read latency due to the slower communication speed between processors and the shared memory, which can be mitigated by migrating frequently accessed data to dedicated memory devices.
Innovation Solution
A shared memory device with a snoop filter circuit and migration management circuit that determines cache line hotness based on entry access counts and triggers data migration to dedicated memory devices before invalidation, ensuring faster access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in shared memory device, then memory accessibility is improved, but read latency increases when cache line is invalidated
Solution Approach 1:
The system performs preliminary action by migrating hot cache lines to dedicated memory devices before they are invalidated. The migration management circuit identifies hot cache lines based on access patterns and triggers data migration proactively, so that when invalidation occurs, the data is already available in the dedicated memory device, eliminating read latency.
Solution Approach 2:
The system extracts frequently accessed hot data from the shared memory device and places it in dedicated memory devices. By separating hot data from cold data through selective migration, the system maintains fast access for frequently used data while preserving the shared memory architecture for general access.
2Reliability
If cache line is invalidated to maintain memory consistency, then data correctness is improved, but read latency increases
Solution Approach 1:
The system performs preliminary action by migrating hot cache lines to dedicated memory devices before they are invalidated. The migration management circuit identifies hot cache lines based on access patterns and triggers data migration proactively, so that when invalidation occurs, the data is already available in the dedicated memory device, eliminating read latency.
Solution Approach 2:
The dedicated memory device acts as an intermediary between the shared memory device and the cache line. When a cache line is invalidated, instead of immediately reading from the shared memory device, the system checks the dedicated memory device first, which may already contain the migrated data, thus mediating the read operation to reduce latency.
3Speed
If data migration is performed to reduce read latency, then access speed is improved, but device complexity increases
Solution Approach 1:
The system performs self-service by using the shared memory device's own snoop filter circuit and migration management circuit to automatically identify and migrate hot data. The snoop filter circuit monitors access patterns and the migration management circuit autonomously decides when migration is needed, eliminating the need for external control mechanisms and reducing overall system complexity.
Solution Approach 2:
The system merges the snoop filter circuit and migration management circuit into the shared memory device, combining data monitoring and migration control functions in one location. This integration reduces system complexity by eliminating separate control components and simplifying the overall memory architecture.
Data Source
AI summary
A shared memory device includes a memory bank that stores first raw data corresponding to a first cache line stored in a first processor among processors, a snoop filter circuit including a first snoop filter entry corresponding to the first cache line and a first entry access count corresponding to the first snoop filter entry, and a migration management circuit that determines a hotness of the first cache line based on the first entry access count and issues a migration request for the first raw data to the first processor based on the hotness.