Shared Memory Atomic Operations Across Coherence Domains
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Solution Overview
Problem
Conventional approaches for coordinating atomic accesses across multiple virtual hierarchies in computing systems result in high latency and poor performance due to the use of networking semantics, making it challenging to efficiently share memory across independent hosts.
Innovation Solution
Implementing a control circuit with circuitry to perform memory sharing and atomic access using load-store semantics, which includes submission queues for requests, directory structures for cache coherency, and back invalidate commands to manage coherency conflicts, allowing for low-latency and high-bandwidth memory sharing and atomic operations across multiple coherence domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional networking semantics are used for coordinating atomic accesses across multiple virtual hierarchies, then system compatibility and ease of operation are maintained, but latency increases and performance deteriorates
Solution Approach 1:
The patent introduces a switch device as an intermediary between multiple hosts to coordinate atomic memory accesses. The switch device implements a directory structure that tracks ownership of memory locations and coordinates access requests, replacing the need for hosts to use complex networking semantics directly. This intermediary approach reduces latency by handling coordination centrally while maintaining system compatibility.
Solution Approach 2:
The patent segments the memory system into multiple coherence domains, each associated with a specific host or virtual hierarchy. The directory structure is segmented to track ownership within each domain independently. This segmentation allows atomic operations to be coordinated locally within domains rather than requiring global networking semantics, reducing latency while maintaining ease of operation through modular design.
2Productivity
If memory sharing across independent hosts is implemented using conventional approaches, then adaptability and versatility are improved, but performance and bandwidth are reduced
Solution Approach 1:
The switch device acts as an intermediary that enables memory sharing across independent hosts while maintaining high bandwidth. It implements a directory structure that efficiently tracks and manages shared memory access rights, allowing multiple hosts to access the same memory locations with high-speed interconnects rather than through slower networking semantics. This achieves both high productivity and adaptability.
Solution Approach 2:
The patent introduces a new dimension of memory sharing by implementing cross-host coherence domains. Instead of limiting memory sharing within single-host boundaries, the directory structure enables memory locations to be shared across multiple hosts simultaneously, creating a multi-dimensional memory access topology that increases both bandwidth and versatility.
3Reliability
If atomic accesses are coordinated across multiple virtual hierarchies using traditional methods, then reliability is maintained, but latency and operational efficiency deteriorate
Solution Approach 1:
The switch device serves as a reliable intermediary that ensures atomic access correctness across multiple virtual hierarchies. The directory structure maintains ownership information and coordinates access requests to guarantee atomicity, while the high-speed interconnect eliminates the latency associated with traditional networking-based coordination methods.
Solution Approach 2:
The patent implements preliminary action by having the directory structure pre-establish ownership records for memory locations before atomic operations occur. When a host wants to perform an atomic operation, the ownership information is already available in the directory, allowing immediate coordination without the latency of establishing coherence protocols in real-time. This preliminary setup maintains reliability while reducing coordination latency.
Data Source
AI summary
In an embodiment, an apparatus for memory access may include: a memory comprising at least one atomic memory region, and a control circuit coupled to the memory, The control circuit may be to: for each submission queue of a plurality of submission queues, identify an atomic memory location specified in a first entry of the submission queue, wherein each submission queue is to store access requests from a different requester; determine whether the atomic memory location includes existing requester information; and in response to a determination that the atomic memory location does not include existing requester information, perform an atomic operation for the atomic memory location based at least in part on the first entry of the submission queue. Other embodiments are described and claimed.


