Shared Memory Command Bus to Cut Pin Count and Footprint
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems with separate command buses for each device increase the overall footprint and design complexity, leading to inefficiencies and environmental concerns due to increased material usage and waste.
Innovation Solution
Implementing a shared command bus architecture between a memory system controller and multiple memory devices, reducing the number of pins and allowing for a more compact design with improved flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate command buses are used for each memory device, then command communication reliability is improved, but the overall footprint and design complexity increase
Solution Approach 1:
The patent merges multiple separate command buses into a single shared command bus that serves multiple memory devices. The command bus is shared among first and second memory devices, reducing the total number of command bus pins from two separate buses to one common bus, thereby reducing design complexity while maintaining communication reliability through proper signal management.
Solution Approach 2:
The command bus is designed with universal functionality to serve multiple memory devices simultaneously. The same command bus pins are used to communicate with both first and second memory devices, allowing the command bus to perform multiple functions and reducing overall system complexity while maintaining reliable command delivery to each device.
2Reliability
If separate command buses are used for each memory device, then command signal integrity is improved, but the physical size and material usage increase
Solution Approach 1:
Multiple separate command bus physical connections are merged into a single shared command bus structure. Instead of having separate physical traces and pins for each memory device, the patent combines them into one common command bus that physically connects to multiple devices, reducing the overall area required for command bus routing while maintaining signal integrity through proper design.
3Adaptability or versatility
If separate command buses are used for each memory device, then device independence is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The command bus is designed as a universal interface that can independently communicate with multiple different memory devices. Each memory device maintains its independence and ability to receive commands, but they all share the same command bus infrastructure, simplifying manufacturing by reducing the number of unique command bus connections that need to be fabricated and tested.
Data Source
AI summary
Methods, systems, and devices for shared command bus architecture for memory systems are described. A memory system communicating according to a separate command address (SCA) protocol may implement a shared command bus between a memory system controller and multiple memory devices. The memory system may include processing circuitry coupled with a first memory device and a second memory device. The processing circuitry may be configured to communicate first data with a first memory device via a first data bus and may be configured to communicate second data with a second memory device via a second data bus. The memory system may include a command bus in which each pin of the command bus is common to the first memory device and the second memory device, such that each pin is configured to communicate signaling associated with commands to the first memory device and the second memory device.