Shared Memory Controller Beat-Level Arbitration
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Solution Overview
Problem
In multi-core system-on-a-chip (SOC) architectures, the shared memory controller often acts as a bottleneck due to its inability to efficiently manage concurrent read/write transactions across multiple processing cores and memory blocks, leading to increased latency and performance degradation.
Innovation Solution
A shared memory controller that concurrently scans and divides read/write commands into beat-level commands, arbitrates them based on priority, and dispatches them to shared memory blocks, allowing for simultaneous access and reducing latency by employing a command scanner and multiple read/write arbiters to manage transactions at a finer granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shared memory controller is used to regulate data flow among multiple processing cores and memory blocks, then memory access control is achieved, but the controller becomes a bottleneck causing increased latency and performance degradation
Solution Approach 1:
The shared memory is divided into multiple physical blocks, and the controller uses multiple independent read/write arbiters (one per memory block) to simultaneously handle multiple transactions. This segmentation allows parallel processing of memory access requests, reducing the bottleneck effect and access latency while maintaining reliable control.
2Adaptability or versatility
If the shared memory controller handles concurrent read/write transactions from multiple processing cores, then multi-core functionality is supported, but the controller complexity increases
Solution Approach 1:
The controller is segmented into multiple independent read/write arbiters, each responsible for a specific memory block. This modular architecture supports multiple processing cores concurrently while keeping each arbiter's complexity manageable through specialization.
Solution Approach 2:
The controller transitions from sequential transaction handling to concurrent beat-level command processing. By dividing transactions into beats and processing them at the beat level rather than the transaction level, the controller achieves parallelism across multiple dimensions, supporting multi-core functionality without proportionally increasing complexity.
3Device complexity
If transactions are processed at the transaction level, then simplicity is maintained, but concurrency and throughput are limited
Solution Approach 1:
Transactions are segmented into smaller beat-level commands, allowing multiple beats from different transactions to be processed concurrently by different arbiters. This segmentation increases throughput while maintaining relative simplicity through systematic division of work.
Solution Approach 2:
The processing granularity shifts from the transaction dimension to the beat dimension. This dimensional change enables fine-grained parallelism where beats from multiple transactions can be interleaved and processed simultaneously, dramatically increasing throughput without requiring complex reconfiguration of the basic processing units.
Data Source
AI summary
Disclosed herein are a shared memory controller and a method of controlling a shared memory. An embodiment method of controlling a shared memory includes concurrently scanning-in a plurality of read/write commands for respective transactions. Each of the plurality of read/write commands includes respective addresses and respective priorities. Additionally, each of the respective transactions is divisible into at least one beat and at least one of the respective transactions is divisible into multiple beats. The method also includes dividing the plurality of read/write commands into respective beat-level read/write commands and concurrently arbitrating the respective beat-level read/write commands according to the respective addresses and the respective priorities. Concurrently arbitrating yields respective sequences of beat-level read/write commands corresponding to the respective addresses. The method further includes concurrently dispatching the respective sequences of beat-level read/write commands to the shared memory, thereby accessing the shared memory.