Shared Memory Controller Bus Arbitration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microcontroller integrated circuits face challenges in efficiently utilizing data bus terminals for accessing various memory devices of different widths, leading to suboptimal memory data bus bandwidth and utilization.
Innovation Solution
A novel memory controller mechanism that operates in two modes: one for simultaneous independent narrow accesses and another for wider accesses by dynamically switching and sharing data bus terminals and conductors between memory controllers, allowing for increased bandwidth and utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate data buses are used for each memory controller, then each controller can perform accesses simultaneously, but the device complexity and loss of substance increase due to unused bus terminals
Solution Approach 1:
The patent merges the data bus terminals of multiple memory controllers into a shared resource. Specifically, memory controllers are configured to share common data bus terminals (e.g., D0-D15) with other masters in the system, allowing these terminals to be used by multiple controllers sequentially rather than being dedicated to single controllers. This reduces the total number of physical bus terminals needed while maintaining simultaneous access capability through time-multiplexed arbitration.
Solution Approach 2:
The data bus terminals are designed to serve multiple functions and multiple masters. The same set of data bus terminals can be used by different memory controllers at different times, depending on which controller wins the bus arbitration. This multi-functionality allows the system to achieve high productivity without requiring dedicated separate buses for each controller, thereby reducing material loss.
2Productivity
If dedicated data buses are allocated to each memory controller, then simultaneous independent accesses are enabled, but the device complexity increases
Solution Approach 1:
The patent combines multiple dedicated data bus sets into a shared data bus infrastructure. Instead of providing separate physical data buses for each memory controller, the system uses a common set of data bus terminals that are arbitrated among multiple controllers. This merging approach maintains concurrent access capability through arbitration while significantly reducing the total number of bus terminals and associated complexity.
Solution Approach 2:
The patent introduces a bus arbitration mechanism as an intermediary between multiple memory controllers and the shared data bus terminals. The arbitration logic mediates access requests from multiple controllers, granting bus ownership to the appropriate controller based on priority or round-robin schemes. This intermediary enables simultaneous independent accesses to be coordinated without requiring dedicated physical buses for each controller.
3Loss of substance
If data bus terminals are shared between memory controllers, then bandwidth utilization improves, but the difficulty of detecting and measuring increases due to arbitration requirements
Solution Approach 1:
The patent employs arbitration logic as an intermediary that manages shared data bus terminal access. This arbitration mechanism detects and measures bus usage by monitoring access requests from multiple memory controllers and granting bus ownership accordingly. The arbitration logic includes state machines and control signals that track bus ownership, request status, and grant decisions, making the sharing mechanism detectable and measurable despite the added complexity.
Solution Approach 2:
The bus arbitration system uses feedback mechanisms to manage shared data bus terminals. The arbitration logic receives feedback from memory controllers regarding their access requests and bus availability status, and adjusts bus grant decisions based on this feedback. This feedback loop enables efficient utilization of shared terminals while providing a structured way to detect and measure arbitration behavior through standardized control signals and state transitions.
Data Source
AI summary
A memory controller mechanism is operable in a first mode and a second mode. In the first mode, a first memory controller portion of the mechanism can use a first set of data terminals to perform a first external bus access operation (EBAO) and a second memory controller portion of the mechanism can use a second set of data terminals to perform a second EBAO. The first and second EBAO operations may be narrow accesses that occur simultaneously. In the second mode, one of the controllers can use both the first and second sets of data terminals to perform a wider third EBAO. The memory controller mechanism can dynamically switch between first mode and second mode operations. In situations in which one of the sets of data terminals would not otherwise be used, performing wide accesses in the second mode using the one set of data terminals improves bus utilization.