Shared Memory Data Rate Control via Direct Client Lines

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Solution Overview

Problem

Existing data processing systems face challenges in efficiently managing access to shared memory units, particularly in real-time applications where the delay in allocating bandwidth by a memory arbiter can be too long, and splitting tasks into sub-tasks may not be feasible due to hardware or software design complexities.

Innovation Solution

The system introduces additional control lines between clients to allow direct data rate adaptation, enabling one client to throttle the data rates of others based on internal data requirements, bypassing the arbiter for real-time control and ensuring the most critical clients receive the highest possible data rate supported by the hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a memory arbiter is used to control access to the shared memory unit, then bandwidth allocation and interference avoidance are improved, but the response time for real-time data rate adaptation deteriorates due to arbiter decision-making delays

Engineering Contradiction:
Improvebandwidth allocationVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the bandwidth control function into two parts: the memory arbiter handles overall bandwidth allocation and interference avoidance, while additional control lines enable direct real-time data rate adaptation between clients. This segmentation allows each component to specialize in its strength without the other being a bottleneck.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces additional control lines as an intermediary mechanism between clients and the memory unit. These control lines enable direct communication for real-time data rate adjustments, bypassing the arbiter's decision-making process for time-critical adaptations while maintaining the arbiter's overall coordination role.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If tasks are split into sub-tasks to enable real-time control, then responsiveness is improved, but system complexity increases due to hardware or software design constraints

Engineering Contradiction:
ImproveresponsivenessVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts the real-time data rate control function from the complex task-splitting approach and implements it through dedicated control lines. This extraction allows real-time responsiveness without requiring complex task segmentation logic in the hardware or software design.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent enables clients to directly control their own data rates through the additional control lines, allowing them to self-adjust in real-time based on their immediate needs without requiring complex centralized task management and scheduling.

Inventive Principle:
Principle #25Self-service

3Loss of time

If direct control lines are added between clients for real-time data rate adaptation, then real-time responsiveness is improved, but device complexity increases

Engineering Contradiction:
Improvereal-time responsivenessVSAvoidcontrol line complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent introduces dynamic control lines that can be selectively activated based on real-time data rate requirements. These control lines provide a flexible, adaptable communication path that enables rapid data rate adjustments without requiring a complete redesign of the control architecture.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP2783286B1Data processing system and method of controlling access to a shared memory unit
Publication Date: 2018.04.04 NXP USA INC
  • EP2783286B1 patent drawingFigure 1~2
  • EP2783286B1 patent drawingFigure 3
  • EP2783286B1 patent drawingFigure 4~5

AI summary

A data processing system (10) comprising at least a memory unit (12), a first client (16) connected to the memory unit (12), and a second client connected to the memory unit (12) is proposed. The first client (16) may comprise a first memory access unit (28) and an information unit. The first memory access unit (28) may read data from or write data to the memory unit (12) at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit (34) and a data rate limiting unit (48). The second memory access unit (34) may read data from or write data to the memory unit (12) at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit (28) may, for example, read data packets sequentially from the memory unit (12), and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.