Shared Memory Layout for Multi-CPU Vehicle Display Synchronization

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Solution Overview

Problem

Existing vehicle device control methods face challenges in reducing the load on cache memory and bus due to increased size and definition of display devices, leading to potential delays and unsynchronized displays.

Innovation Solution

A vehicle device with multiple CPU modules, cache memories, a specifying unit to identify shared regions, and a region arrangement unit to allocate these shared regions in the main memory, allowing for efficient sharing and synchronization of surfaces across CPU modules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If display device size and definition are increased, then display quality is improved, but cache memory load and bus load increase

Engineering Contradiction:

Improvedisplay qualityVSAvoidcache memory load

Core Design Contradiction:

Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent segments the memory system into cache memories (for high-speed access) and main memory (for large capacity), with a memory control unit that intelligently manages data placement and retrieval between these segments based on access patterns and data sharing requirements

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory control unit acts as an intermediary between the CPU module and the memory system, managing data transfer between cache memories and main memory, and coordinating access from multiple CPU modules to reduce bus contention and cache load

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If display device size and definition are increased, then display quality is improved, but bus load increases causing delays

Engineering Contradiction:

Improvedisplay qualityVSAvoiddisplay synchronization delay

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-loading data into cache memories before it is needed, and by the memory control unit anticipating future access patterns to proactively manage data placement, reducing the need for time-critical data retrieval operations

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a hierarchical memory architecture that adds a temporal dimension to memory access, allowing data to be cached across multiple time steps and accessed from optimal locations, thereby reducing bus contention and access delays

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If multiple CPU modules share memory, then processing capability is improved, but synchronization complexity increases

Engineering Contradiction:

Improveprocessing capabilityVSAvoidsynchronization complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory control unit performs multiple functions including addressing, data transfer control, cache coherence management, and synchronization coordination, serving as a universal controller that simplifies the overall system architecture despite multiple CPU modules

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements feedback mechanisms where the memory control unit monitors access patterns from multiple CPU modules and adjusts data placement and retrieval strategies to maintain cache coherence and synchronization, using status information from the memory system to guide subsequent operations

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12208812B2Vehicle device and vehicle device control method

Publication Date: 2025.01.28 DENSO CORP

AI summary

A vehicle device includes a plurality of CPU modules, a plurality of cache memories respectively provided for the plurality of CPU modules, a specifying unit configured to specify a shared region shared by the plurality of CPU modules, and a region arrangement unit configured to arrange the shared region specified by the specifying unit in a main memory.