Shared Memory Controller DMA Path for AXI Bottleneck Relief
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Solution Overview
Problem
AXI interconnect traffic in System-on-Chip (SoC) architectures creates performance bottlenecks due to competing requests from processing cores, DMA controllers, and peripheral devices, leading to extended transaction completion times and reduced memory transfer efficiency.
Innovation Solution
A shared memory controller (SMC) with direct memory access (DMA) architecture is implemented within the SoC, allowing memory-to-memory operations to bypass the AXI interconnect through an internal path, utilizing a DMA interconnect that directs data transfers directly between memory banks, and incorporating a MBIST controller for dual-path memory testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If AXI interconnect is used for memory access, then standardized protocol transactions are enabled, but performance bottlenecks occur due to arbitration delays and extended transaction completion times
Solution Approach 1:
The memory access path is segmented into two independent routes: AXI interconnect for standardized protocol transactions and OCM-internal path for high-speed memory-to-memory operations. This segmentation allows each path to serve its specific function optimally without interfering with the other, resolving the contradiction between protocol standardization and transfer efficiency.
Solution Approach 2:
The shared memory controller acts as an intermediary that directs memory-to-memory operations through the OCM-internal path while maintaining AXI interconnect for other transactions. This intermediary function enables efficient data transfer by routing operations through the appropriate path, eliminating arbitration delays for internal memory operations.
2Ease of operation
If shared memory controller manages all memory access requests, then centralized control is achieved, but arbitration delays accumulate during high-traffic scenarios
Solution Approach 1:
Memory access requests are segmented into two types: those requiring centralized control via AXI interconnect and those that can proceed directly through OCM-internal path. This segmentation reduces the arbitration burden on the shared memory controller by allowing memory-to-memory operations to bypass the arbitration mechanism entirely.
Solution Approach 2:
The OCM-internal path enables self-service data transfer between memory banks without requiring intervention from the shared memory controller or AXI interconnect arbitration mechanism. This self-service capability eliminates arbitration delays for internal memory operations while maintaining centralized control for external transactions.
3Reliability
If DMA controller uses AXI interconnect for memory-to-memory operations, then protocol compliance is maintained, but unnecessary data movement through AXI interconnect increases latency
Solution Approach 1:
The data transfer path is segmented based on operation type: AXI interconnect is used for protocol-compliant external memory access while OCM-internal path is used for high-speed internal memory-to-memory transfers. This segmentation maintains protocol compliance where needed while eliminating unnecessary latency for internal operations.
Solution Approach 2:
Different quality characteristics are applied to different parts of the data path: AXI interconnect provides standardized protocol support for external access, while OCM-internal path provides optimized low-latency transfer for internal memory operations. This local quality differentiation allows each path to be optimized for its specific function without compromising overall system reliability.
Data Source
AI summary
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.