Shared Memory Dual Video Processor Bandwidth Optimization
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Solution Overview
Problem
Traditional dual video processing chips struggle to produce high-quality video images for multiple channels due to high memory access bandwidth requirements, which limits their ability to handle increased demand for displaying two channels with high video quality, especially with the advent of wider screens and aspect ratios like 16:9.
Innovation Solution
The system reduces memory access bandwidth by implementing a dual video processor with shared memory and processing resources, including time multiplexing, field line buffering, and a blank time optimizer to efficiently manage memory access and distribute bandwidth across multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional dual video processing chips are used to process multiple video channels, then video processing capability is provided, but memory access bandwidth requirements become excessively high, limiting the ability to produce high-quality video images for multiple channels
Solution Approach 1:
The patent segments the video processing pipeline into distinct functional units (video decoders, video processors, field line buffers) that can operate independently and share resources. Multiple video channels are processed through segmented processing stages rather than monolithic processing, allowing memory bandwidth to be distributed across channels in time-division multiplexed fashion.
Solution Approach 2:
The patent merges multiple video channel processing streams into a unified memory architecture where field line buffers serve multiple channels. By combining memory resources and processing units into a shared infrastructure with time-multiplexed access, the system reduces total memory bandwidth requirements while maintaining multiple high-quality video output streams.
2Manufacturing precision
If 3-D video processing operations (de-interlacing, noise reduction, frame rate conversion) are implemented on multiple video channels, then video quality is improved, but memory bandwidth requirements increase proportionally with the number of channels
Solution Approach 1:
The patent implements periodic action through time-division multiplexing where memory resources are allocated to different video channels in periodic time slots. Field line buffers for multiple channels are updated and accessed in alternating sequences, allowing 3-D processing operations on multiple channels to share memory bandwidth periodically rather than simultaneously, thus reducing total bandwidth requirements while maintaining video quality.
3Device complexity
If the second channel video pipe implements only 2-D video processing operations to reduce costs, then device complexity is reduced, but video quality of the second channel deteriorates compared to the first channel
Solution Approach 1:
The patent makes the video processing pipeline universal by enabling the same processing units (video decoders, video processors, field line buffers) to handle multiple video channels with equal capability. The shared memory architecture and time-multiplexed access allow both first and second channel video pipes to implement full 3-D processing operations (de-interlacing, noise reduction, frame rate conversion) rather than limiting the second channel to 2-D operations, thus maintaining equal video quality across channels while reducing overall device complexity through resource sharing.
Data Source
AI summary
The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.