Shared Memory Execution Counter for Network Load Reduction
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Solution Overview
Problem
The existing information processing devices with shared memory and multiple processors face a heavy network load due to the frequent transmission of acknowledgments for each Store instruction, leading to increased hardware requirements and network congestion.
Innovation Solution
Implementing an execution counter in the shared memory that counts completed Store instructions and transmits this count asynchronously to the processor, reducing the frequency of acknowledgment transmissions and optimizing network usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the shared memory transmits an acknowledgment for each Store instruction to the Release side processor, then the memory order guarantee is ensured, but the network load becomes heavy
Solution Approach 1:
The patent merges multiple acknowledgment transmissions into a single notification by using an execution counter that accumulates the number of completed Store instructions. Instead of sending individual acknowledgments for each Store instruction, the shared memory notifies the Release side processor only when the execution counter reaches a threshold value, thereby combining multiple acknowledgment functions into one network transaction and reducing overall network load while maintaining memory order guarantee
Solution Approach 2:
The patent implements preliminary action by having the shared memory continuously update the execution counter in the background as Store instructions complete, before any notification is sent to the Release side processor. This allows the system to prepare acknowledgment information in advance and only transmit it when necessary, avoiding frequent network transmissions while ensuring that acknowledgment data is ready when the processor needs it
2Object-generated harmful factors
If the frequency of acknowledgment transmission is reduced, then the network load is reduced, but the global visibility of invalidation requests may be compromised
Solution Approach 1:
The patent implements a feedback mechanism where the Release side processor monitors the execution counter value and compares it against a threshold. When the counter reaches the threshold, the processor receives a notification and can then issue a Store Fence instruction to ensure global visibility. This feedback loop allows the system to reduce notification frequency while maintaining reliability, as the processor actively monitors counter updates and triggers synchronization only when necessary
Solution Approach 2:
The patent introduces dynamic adaptability by allowing the threshold value for notification to be configurable and adjustable based on system conditions. The notification frequency and timing can be dynamically optimized to balance network load reduction with the need for global visibility, enabling the system to adapt to different workloads and performance requirements while maintaining memory order guarantees
Data Source
AI summary
On receiving a Store instruction from a Release side processor, a shared memory transmits a cache invalidation request to an Acquire side processor, increases the value of an execution counter, and transmits the count value to the Release side processor asynchronously with the receiving of the Store instruction. The Release side processor has: a store counter which increases its value when the Store instruction is issued and, when the count value of the execution counter is received, decreases its value by the count value; and a wait counter which, when the store counter has come to indicate 0, sets a value indicating a predetermined time and decreases its value every unit time. The Release side processor issues a Store Fence instruction to request for a guarantee of completion of invalidation of the cache of the Acquire side processor when both the counters have come to indicate 0.