Shared Memory Architecture for Multi-GNSS Receiver Systems
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Solution Overview
Problem
Conventional GNSS receivers face inefficiencies in memory allocation, leading to increased size and cost due to dedicated memory devices for each functional stage, especially when supporting multiple GNSS systems.
Innovation Solution
A shared memory architecture where multiple functional stages within a receiver system share a memory space, dynamically allocated by a memory controller based on available storage and priority of GNSS systems, allowing efficient buffering of processing data across different GNSS systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated memory devices are assigned to each functional stage, then each functional stage has guaranteed memory resources, but the overall system size and cost increase due to memory allocation inefficiency
Solution Approach 1:
The patent merges multiple dedicated memory devices into a single shared memory device that serves multiple functional stages. The shared memory device includes a memory space that is commonly shared by first and second functional stages, allowing them to buffer processing data from different transmitter systems simultaneously. This consolidation reduces the total quantity of memory components while maintaining reliable memory resources for each functional stage through dynamic allocation.
Solution Approach 2:
The shared memory device is designed with multi-functionality to serve multiple functional stages for different transmitter systems. The memory space can be dynamically allocated to buffer processing data from various sources including GPS, Galileo, and GLONASS systems, making the memory resource universal rather than dedicated to a single function or system.
2Ease of operation
If dedicated memory devices are assigned to each functional stage, then memory access is simple and direct, but the number of memory devices and system complexity increase
Solution Approach 1:
Multiple memory devices are merged into a single shared memory device with a unified memory space. This reduces the number of memory components in the system while providing standardized access interfaces that maintain operational simplicity for functional stages.
Solution Approach 2:
The patent introduces a memory controller as an intermediary between functional stages and the shared memory device. The memory controller manages memory space allocation and data buffering operations, providing a simplified access mechanism that handles the complexity of shared resource management transparently to the functional stages.
3Quantity of substance
If multiple memory devices are used for different transmitter systems, then memory resources are sufficient for all systems, but memory utilization efficiency decreases
Solution Approach 1:
The patent implements dynamic memory allocation where the memory space in the shared memory device can be flexibly allocated based on the actual needs of different transmitter systems. The memory controller dynamically adjusts the portion of memory space assigned to each system, ensuring that memory capacity is sufficient for all systems while maximizing utilization efficiency by allocating only the necessary resources to each functional stage.
Data Source
AI summary
A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system respectively. The shared memory device has a memory space, allocated to be commonly shared by the first functional stage and the second functional stage, for buffering processing data generated from the first functional stage or the second functional stage.