Shared Memory Interconnection Network for Tightly-Coupled Multiprocessors
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Solution Overview
Problem
Existing multiprocessor computers face inefficiencies in allowing tens of processing cores to concurrently access random addresses in a shared memory system with bandwidth and latency comparable to single-core local memory access, due to cumbersome interconnection networks and the burden of synchronization and scheduling activities.
Innovation Solution
A shared memory system with a separate read and write network, utilizing logarithmic multistage networks in parallel, which computes paths between processing cores and memory banks at every clock cycle, supports simple read and write operations, and exploits memory locality to increase bandwidth, reducing delays and conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a shared memory system is used to support tens of processing cores, then the system can achieve parallel computation, but the bandwidth and latency become insufficient compared to single-core local memory access
Solution Approach 1:
The shared memory system is divided into multiple memory banks (B1, B2, ..., Bk) that can be accessed independently. Each memory bank operates as a separate entity with its own access interface, allowing multiple processing cores to simultaneously access different banks without interfering with each other. This segmentation enables the shared memory system to provide bandwidth comparable to local memory by allowing parallel access to multiple banks.
Solution Approach 2:
A dedicated interconnection network acts as an intermediary between processing cores and memory banks. This interconnection network is specifically designed to provide low-latency, high-bandwidth communication paths, serving as a specialized mediator that optimizes the access speed between cores and the segmented memory banks, achieving performance comparable to local memory access.
2Adaptability or versatility
If a complicated interconnection network is used to connect processing cores to memory banks, then more cores can be supported, but the device complexity increases and performance decreases
Solution Approach 1:
The interconnection network is segmented into multiple independent paths or stages, where each segment handles a specific portion of the core-to-memory bank routing. This segmentation allows the network to scale to support more cores by adding segments rather than increasing the complexity of a monolithic network structure.
Solution Approach 2:
The interconnection network is organized as a multistage network where data flows through multiple dimensions or stages of routing. Instead of a single complex routing dimension, the network uses multiple simpler stages (e.g., stage 1 routes to intermediate nodes, stage 2 routes to final banks), transforming a complex single-dimension problem into multiple simpler dimensions.
3Ease of operation
If synchronization and scheduling activities are performed through the shared memory system, then coordination between cores is achieved, but the shared memory efficiency deteriorates due to hot spots and atomic operation requirements
Solution Approach 1:
Synchronization and scheduling activities are extracted from the shared memory system and handled by separate dedicated hardware units. This extraction removes the burden of atomic operations and synchronization primitives from the memory path, allowing the shared memory system to focus on efficient data access while synchronization is handled independently through specialized circuits.
Solution Approach 2:
Dedicated synchronization units act as intermediaries between processing cores, handling all coordination activities outside the shared memory path. These intermediary units manage atomic operations and synchronization without requiring shared memory involvement, preventing hot spots and maintaining high memory access efficiency.
Data Source
AI summary
A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement. It returns an approval reply to every core whose initiative of accessing memory leads to the successful establishment of a path and is fulfilled, or a rejection reply to every core whose initiative is not fulfilled.