Shared Memory Interface Circuit for Multi-Processor Data Exchange
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Solution Overview
Problem
In mobile devices, the separation and processing of data between application processors and connectivity processors are inefficient due to independent operation and reliance on chip-to-chip interfaces, leading to increased power consumption and reduced performance.
Innovation Solution
A multi-processor system with a common memory and memory interface circuit that allows both processors to access and share data directly, using DMA units and cipher/decipher modules to manage and process data within the memory interface, reducing the need for external bus interactions and enhancing data processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the application processor and connectivity processor operate separately as independent systems with chip-to-chip interface, then each processor can function independently, but data exchange between processors becomes inefficient and increases power consumption
Solution Approach 1:
The patent merges the application processor and connectivity processor into a single system-on-chip (SoC) with a shared memory space. This integration eliminates the need for chip-to-chip interfaces, enabling direct memory access between processors and significantly improving data exchange efficiency while reducing power consumption.
Solution Approach 2:
The patent introduces a memory interface circuit as an intermediary component that manages data exchange between the application processor and connectivity processor through the shared memory. This mediator enables efficient communication by providing a standardized interface and memory management capabilities without requiring direct processor-to-processor connections.
2Speed
If separate memory systems are used for each processor, then memory independence is maintained, but memory access time increases and data sharing becomes inefficient
Solution Approach 1:
The patent combines separate memory systems into a single shared memory space that is accessible by both the application processor and connectivity processor. This unified memory architecture reduces memory access time and simplifies data sharing while maintaining logical separation through memory management techniques.
Solution Approach 2:
The shared memory is segmented into different regions or spaces that are logically assigned to different processors. This segmentation allows each processor to access its designated memory space efficiently while enabling controlled data sharing through the memory interface circuit, thus reducing access time without creating a completely monolithic memory system.
3Productivity
If chip-to-chip interface is used for data exchange, then processor independence is maintained, but the interface complexity increases and performance is reduced
Solution Approach 1:
The patent integrates the application processor and connectivity processor into a single chip, eliminating the chip-to-chip interface entirely. This merger removes the interface complexity and enables direct internal communication pathways, significantly improving processing performance and data exchange efficiency.
Solution Approach 2:
The patent extracts and removes the chip-to-chip interface from the system architecture by integrating both processors on the same chip. This extraction eliminates the performance bottleneck and complexity associated with external interfaces, replacing them with internal communication pathways.
Data Source
AI summary
A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.