Shared Memory Interleaving for Multiport Switch Throughput Management
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Solution Overview
Problem
In multiport switches, achieving efficient packet storage in shared memory while maintaining low latency is hindered by the need to match input and output throughput of each port with the shared memory, limiting configuration variability and requiring padding data, which decreases efficiency.
Innovation Solution
A shared memory system with multiple memory banks and a controller that writes data sequentially across memory blocks, using interleaving to manage throughput differences between ports and memory, allowing for efficient data transfer without matching port throughputs to memory throughputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the input and output throughput of each port is set to match the input and output throughput of the shared memory per port, then the efficiency of storing operations on the shared memory is improved, but the variation of the configuration of the switch is significantly limited
Solution Approach 1:
The shared memory is divided into multiple memory banks (e.g., 6 memory banks), and data is distributed across these banks in an interleaved manner. This segmentation allows the system to handle throughput differences by parallelizing operations across multiple banks, thereby maintaining high storing efficiency without requiring port throughputs to exactly match memory throughput.
Solution Approach 2:
The system dynamically manages data transfer by introducing a buffer that can absorb throughput differences between ports and shared memory. The buffer size and timing are adjusted dynamically to accommodate varying port throughputs, enabling flexible switch configurations while maintaining efficient memory utilization.
2Loss of time
If memory interleaving is used to improve packet switching speed, then the latency is shortened, but padding data must be inserted to match data rates, which decreases the efficiency of storing operations on the memory
Solution Approach 1:
The system uses partial interleaving where data from multiple ports is distributed across memory banks only when needed, rather than forcing complete rate matching. This allows the system to achieve low latency through selective parallel access to memory banks without inserting excessive padding data, thereby maintaining high storing efficiency.
Solution Approach 2:
A buffer is introduced as an intermediary between the ports and the shared memory. This buffer absorbs the rate differences and allows memory interleaving to proceed without requiring padding, as the buffer temporarily holds data until the memory is ready to accept it, thus maintaining both low latency and high efficiency.
3Quantity of substance
If the number of ports in a switch is increased, then the total input and output throughput of the ports increases, but the input and output throughput of the shared memory per port must be increased to an integral multiple, which limits configuration flexibility
Solution Approach 1:
The shared memory is segmented into multiple independent banks that can be accessed in parallel. When the number of ports is increased, the system can distribute data across these segmented banks without requiring the memory throughput per port to increase to an integral multiple, thus maintaining configuration flexibility while supporting higher port counts.
Solution Approach 2:
The memory bank structure is designed to be universal, where each bank can handle data from any port. This multi-functional design allows the system to accommodate varying numbers of ports with different throughput requirements without requiring specific integral multiple relationships, thereby enabling flexible configurations.
Data Source
AI summary
A shared memory system including: a shared memory includes a plurality of memory banks; a plurality of input ports; a plurality of input buffers; and a controller for controlling writing-into and reading out of the shared memory and for transferring data from each of the input buffers to the shared memory, wherein when one of the memory banks is cycled back next to the starting memory bank, another memory block is to be selected next for writing the remainder of a series of data, said controller controlling each of the input buffers to transfer a plurality of series of data to the shared memory successively with a time gap while switching to said another memory block, said controller offsetting a start memory bank in said another block for start writing the remainder of the series of data by an amount of memory banks corresponding to the time gap.