Shared Memory Link Protocol for Low-Latency Node Memory Access
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Solution Overview
Problem
Existing interconnect architectures in computing systems face challenges in efficiently managing high-performance computing demands, particularly in server environments, where communication between multiple processors and devices is critical, and traditional methods for memory sharing between nodes introduce significant latency and inefficiencies.
Innovation Solution
Implementing a shared memory and I/O architecture that allows nodes to access memory using load/store semantics through a low-latency shared memory link protocol (SML), which overlays existing protocols like PCIe, enabling efficient memory sharing and reduced latency across multiple nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional protocol stacks are used for memory access between nodes, then compatibility and standardization are improved, but latency and access efficiency deteriorate
Solution Approach 1:
The patent segments the protocol processing into two parts: a simplified low-latency transport layer for actual data transfer, and the full protocol stack handled by endpoint devices. This segmentation allows critical memory access paths to bypass complex protocol processing while maintaining compatibility through standardized endpoints.
Solution Approach 2:
The shared memory link protocol acts as an intermediary layer between nodes, providing a simplified communication mechanism that overlays existing protocols like PCIe. This intermediary enables direct memory access semantics while the underlying protocol stack handles compatibility requirements.
2Reliability
If multiple protocol layers are used for reliable communication, then reliability and error handling are improved, but processing overhead and complexity increase
Solution Approach 1:
The patent extracts the complex protocol processing requirements from the memory access path and relocates them to endpoint devices. The shared memory link protocol retains only the essential transport functions needed for low-latency access, while reliability mechanisms are handled by the endpoint protocol stacks.
3Adaptability or versatility
If existing interconnect protocols are used without modification, then standardization is maintained, but performance optimization for shared memory semantics is lost
Solution Approach 1:
The patent merges the benefits of simplified shared memory semantics with existing protocol infrastructure. The SML protocol combines load/store memory semantics with PCIe transport, allowing direct memory access efficiency while maintaining compatibility through the underlying protocol stack.
Data Source
AI summary
A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.