Shared Memory Links for Low-Latency Node-to-Node I/O
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Solution Overview
Problem
Existing interconnect architectures in computing systems face challenges in efficiently managing high-performance computing demands, particularly in server environments, where communication between multiple processors and devices is critical but often limited by latency and bandwidth constraints, especially when sharing memory and I/O services across nodes.
Innovation Solution
Implementing a shared memory architecture that allows for load/store (LD/ST) memory semantics between independent nodes using a low-latency shared memory link (SML) protocol, such as Scalable Memory Interconnect (SMI3), which bypasses traditional protocol stacks to facilitate direct memory access and I/O communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional protocol stacks are used for memory sharing between nodes, then system compatibility and reliability are maintained, but latency increases and bandwidth efficiency decreases
Solution Approach 1:
The patent extracts the memory sharing functionality from the traditional protocol stack by implementing a dedicated shared memory link (SML) that operates independently from conventional network protocols. This allows direct memory access between nodes without traversing multiple protocol layers, thereby reducing latency while maintaining system compatibility through the hybrid architecture that combines SML with traditional protocols for non-memory operations.
2Power
If multiple sockets are used to increase processing power, then computing capability improves, but interconnect communication burden increases
Solution Approach 1:
The shared memory link protocol is designed to handle multiple types of communication operations universally - both memory sharing operations and traditional I/O operations can traverse the same physical link. This multi-functionality allows the system to efficiently manage communications between multiple sockets by routing memory operations directly while allowing other operations to use traditional protocols, thereby maintaining high processing power scalability without proportionally increasing communication burden.
3Speed
If direct memory access is implemented between nodes, then bandwidth efficiency and speed improve, but system complexity and fault isolation challenges increase
Solution Approach 1:
The system architecture is segmented into distinct functional domains: each node maintains its own independent fault domain for isolation, while a centralized or distributed memory controller manages the shared memory link. This segmentation allows direct memory access to proceed at high speed while containing complexity management - fault isolation is maintained through node independence, and resource coordination is handled by the memory controller layer, preventing complexity from propagating throughout the entire system.
Data Source
AI summary
A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.