Configurable Shared Memory Mapping for Neural Network Cores
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Solution Overview
Problem
Neural network devices face challenges in efficiently managing memory requirements for various applications due to irregular memory access times and high area costs, leading to inefficient VLSI floorplans and substantial silicon footprint.
Innovation Solution
A neural network device with a configurable memory mapping unit that assigns physical memory sections dynamically based on application needs, using single-ported memory banks and a memory-interface module to manage access conflicts, allowing flexible configuration of logical memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate physical memories are provided for different storage purposes (event queue, state memory, weight memory, connectivity memory), then memory access times are minimized, but the total memory area and silicon footprint increase substantially
Solution Approach 1:
The patent merges multiple separate physical memories (event queue memory, state memory, weight memory, connectivity memory) into a single shared physical memory structure. This consolidation reduces the total memory area and silicon footprint while maintaining efficient access through a configurable memory mapping unit that dynamically assigns memory regions based on application needs.
Solution Approach 2:
The patent implements dynamic memory allocation through a configurable memory mapping unit that can reassign memory regions at runtime. This allows the system to adapt memory distribution to different application requirements, optimizing both access efficiency and area utilization without being constrained by fixed memory partitions.
2Area of stationary object
If a shared multi-port memory is used for all storage purposes, then the silicon footprint is reduced, but memory access times increase due to access conflicts
Solution Approach 1:
The patent segments the shared physical memory into multiple independently accessible memory banks. This segmentation allows simultaneous access to different memory regions by different processor cores or memory interfaces, reducing access conflicts while maintaining a compact silicon footprint compared to fully separate memory structures.
3Adaptability or versatility
If physical memories are sized to accommodate the largest possible application requirements, then arbitrary applications can be supported, but the silicon footprint increases to accommodate peak memory needs
Solution Approach 1:
The patent implements dynamic memory allocation where the memory mapping unit can reconfigure memory region assignments based on the specific application being executed. This allows the system to support arbitrary applications with varying memory requirements without provisioning for peak demands in all directions simultaneously, optimizing silicon footprint while maintaining full application compatibility.
Data Source
AI summary
A neural network device includes a shared physical memory that has a plurality of independently accessible memory sections. The neural network device further includes a data processor core to execute instructions. The instructions include at least one instruction involving multiple memory access operations specifying respective logical memory addresses in a plurality of logical memories. During configuration of the neural network device for a particular application, respective memory sections of the plurality of independently accessible memory sections are assigned to respective logical memories of the plurality of logical memories. In accordance with the configuration, each logical memory address of the respective logical memory addresses is mapped to a physical address by providing an indication of a memory section of the plurality of independently accessible memory sections and a row address within the memory section.