Shared Memory Architecture for Low Latency Node Communication
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Solution Overview
Problem
Current computing systems face challenges in reducing latency and increasing bandwidth when communicating between nodes in a cluster of autonomous servers, particularly due to limitations in memory addressing and data routing protocols.
Innovation Solution
The system employs a distributed memory architecture with a memory manager that partitions each node's memory into local and global memory spaces, using a parallel link input/output port and protocol engine to route data frames between nodes, allowing for efficient data transfer and emulation of Ethernet protocols while reducing workload on CPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional Ethernet-based communication is used between nodes, then system compatibility and ease of operation are maintained, but latency is high and bandwidth is limited
Solution Approach 1:
The memory space of each node is segmented into local memory address space (accessible only by the node's own CPUs) and global memory address space (accessible by CPUs of all nodes). This segmentation enables direct memory access between nodes through the global address space, eliminating the need for traditional message passing protocols and significantly reducing latency while increasing bandwidth.
2Loss of time
If message passing protocols are used for inter-node communication, then system reliability is maintained, but latency increases and bandwidth decreases
Solution Approach 1:
A protocol engine is introduced as an intermediary component that manages communication between CPUs and the parallel link I/O port. The protocol engine handles frame formatting, routing header preparation, and memory address translation, allowing CPUs to communicate efficiently through the global memory address space without direct involvement in protocol details, thus reducing CPU overhead and latency.
3Productivity
If CPUs directly handle all communication protocols and data routing, then ease of operation is maintained, but CPU workload increases and productivity decreases
Solution Approach 1:
The protocol engine extracts and handles all protocol-related operations (frame formatting, routing, error checking) from the CPU's responsibility. The parallel link I/O port is designed to operate independently, preparing and transmitting data frames through the global memory address space without CPU intervention, thereby freeing CPU resources for computational tasks and improving overall system productivity.
Data Source
AI summary
Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.