Shared-Memory Packet Processing With Reserved Headroom

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Solution Overview

Problem

Satellite communication systems face challenges in optimizing information transmission over limited resources, particularly due to the scarcity of available frequencies and the rapid growth in information volume, leading to inefficiencies in packet processing and memory usage.

Innovation Solution

The implementation of a shared memory region between the application, operating system, and network interface controller for data packet processing, allowing direct writing and reserving headroom in the memory to avoid costly copy operations, thereby enhancing processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional packet processing methods are used with separate memory regions for network interface controller and application, then memory protection and system stability are maintained, but processing efficiency and throughput are significantly reduced due to costly copy operations

Engineering Contradiction:
Improvepackets processed per secondVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the memory regions of the network interface controller and the application into a single shared memory space, eliminating the need for costly copy operations between separate memory regions. This allows the NIC to directly write packets to memory locations that are immediately accessible to the application, significantly improving processing throughput while maintaining system stability through proper memory management mechanisms.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a descriptor ring as an intermediary structure in the shared memory that manages packet data flow between the NIC and application. The descriptor ring contains metadata about packet locations, lengths, and processing status, allowing the system to track and manage packets in the shared memory without requiring complex protection mechanisms, thus resolving the contradiction between shared memory access and memory management complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If headroom is reserved in shared memory adjacent to data packets, then processing efficiency is improved by avoiding copy operations, but memory space utilization is reduced

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmemory space utilization
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent reserves headroom space in the shared memory buffer before packets are written by the NIC. This preliminary allocation of space adjacent to packet data allows the application to perform processing operations (such as adding headers or modifying packet data) directly in place without requiring additional copy operations. The headroom acts as pre-allocated workspace that improves processing efficiency while the memory management system tracks and reuses this space efficiently.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple data packets are processed concurrently in shared memory, then throughput is improved, but memory access conflicts and data integrity issues increase

Engineering Contradiction:
ImprovethroughputVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the shared memory into multiple independent buffer regions, each with its own descriptor entry in the descriptor ring. Each buffer region can be independently allocated to the NIC and accessed by the application without interfering with other packets. This segmentation allows multiple packets to be processed concurrently in parallel while maintaining data integrity through isolated memory spaces, resolving the contradiction between high throughput and reliable data management.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250293996A1Efficient packet processing in a shared memory region
Publication Date: 2025.09.18 KRATOS INTEGRAL HOLDINGS LLC
  • US20250293996A1 patent drawing
  • US20250293996A1 patent drawing
  • US20250293996A1 patent drawing

AI summary

Described herein are systems, methods, and other techniques for processing data packets at a compute infrastructure. An application running on the compute infrastructure allocates a region of a memory for a network interface controller to write or read inbound or outbound data packets. A data packet is received at the network interface controller. The data packet is directly written to the region of the memory. A section of the region of the memory adjacent to the data packet is reserved as headroom such that a memory address occupied by the data packet is adjacent to a memory address occupied by the headroom. The application processes the data packet at the region of the memory by adding data to the data packet, wherein adding the data to the data packet causes the data packet to use at least a portion of the headroom.