Shared Memory Pipeline Parallelism for Multi-Core Processing
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Solution Overview
Problem
Special purpose programmable platforms, such as network processors, expose low-level implementation details that complicate application development and reduce portability, forcing developers to manage processor interconnections and memory hierarchies, which complicates achieving full performance.
Innovation Solution
A computer system utilizing a general purpose multi-core processor with shared memory, allowing parallel frame processing across multiple processing cores through point-to-point communication mechanisms, enabling efficient data transfer between stages without requiring traditional operating system support or specific hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If special purpose programmable platforms are used to increase processing rates, then processing performance is improved, but device complexity increases due to exposed low-level implementation details
Solution Approach 1:
The patent introduces an intermediary layer (the communication mechanism operating in shared memory) that mediates between the processing stages and the underlying hardware architecture. This intermediary abstracts the complex memory hierarchy and processor interconnections, allowing developers to implement parallel processing without directly managing low-level platform details.
Solution Approach 2:
The patent creates a universal communication mechanism that operates across different processing stages and contexts without being tied to specific hardware architecture. This multi-functional approach allows the same mechanism to work across various special purpose platforms, reducing the need for platform-specific implementation details.
2Productivity
If processor interconnections and memory hierarchies are exposed to developers, then processing performance can be optimized, but ease of operation deteriorates due to complicated application development
Solution Approach 1:
The communication mechanism operates autonomously within shared memory, managing its own data transfer and synchronization operations without requiring developer intervention for low-level memory management or interconnection control. The mechanism serves itself by handling communication between processing stages independently.
Solution Approach 2:
The patent introduces an intermediary communication mechanism that handles the complex interactions between processing stages, memory hierarchy, and processor interconnections. This intermediary absorbs the complexity of low-level management while providing a simplified interface to developers.
3Reliability
If traditional operating system support is required for context switching, then reliability is improved, but device complexity increases and portability is reduced
Solution Approach 1:
The patent extracts the context switching and communication management functionality from the operating system layer and implements it directly in the communication mechanism operating in shared memory. This extraction eliminates the dependency on traditional OS support while maintaining reliable context management.
Solution Approach 2:
The communication mechanism acts as an intermediary that provides OS-like context management and coordination services directly at the hardware level, eliminating the need for traditional operating system support while maintaining system reliability.
4Productivity
If platform-specific implementation details are exposed, then processing performance can be maximized, but adaptability deteriorates due to coupling software to specific platform
Solution Approach 1:
The communication mechanism is designed to be universal and platform-independent, operating in shared memory without being tied to specific processor interconnections or memory hierarchy details. This universality allows the same software implementation to achieve high performance across different special purpose platforms.
Solution Approach 2:
The patent segments the processing system into independent processing stages that communicate through a standardized shared memory interface. This segmentation allows each stage to be implemented independently and enables easy porting to different platforms while maintaining optimized performance.
Data Source
AI summary
A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.