Shared Memory Pool for Heterogeneous Data Processing Delays

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Solution Overview

Problem

Existing computing devices face high resource consumption and processing delays due to data movement between separately configured memories of different processors, limiting their ability to handle large-scale data processing efficiently and in real-time.

Innovation Solution

Implementing a shared memory pool with a central processing unit and heterogeneous devices, allowing data processing within a unified memory space without the need for inter-memory data movement, and enabling concurrent or sequential processing by multiple heterogeneous devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If each processor has a separately configured memory, then the computing device can perform service processing by using a plurality of types of computing power provided by the plurality of types of processors, but resource consumption caused by the service processing is high and a service processing delay is high

Engineering Contradiction:
Improvecomputing power typesVSAvoidresource consumption
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent merges multiple separately configured memories into a unified shared memory pool that is accessible by all processor types (CPU, GPU, NPU, etc.). This consolidation eliminates redundant data copies and inter-memory data transfers, thereby reducing resource consumption while maintaining support for multiple computing power types.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared memory pool serves as a universal memory resource that can be accessed by different types of processors for various computing tasks. This multi-functional memory architecture replaces multiple dedicated memories, reducing overall resource consumption while supporting diverse computing operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If each processor has a separately configured memory, then the computing device can perform service processing by using a plurality of types of computing power provided by the plurality of types of processors, but a service processing delay is high

Engineering Contradiction:
Improvecomputing power typesVSAvoidservice processing delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges multiple separately configured memories into a unified shared memory pool that is accessible by all processor types (CPU, GPU, NPU, etc.). This consolidation eliminates redundant data copies and inter-memory data transfers, thereby reducing resource consumption while maintaining support for multiple computing power types.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared memory pool enables continuous data processing by eliminating data transfer delays between separate memories. Data can be processed continuously across different processor types without interruption for memory copying, thereby reducing service processing delay.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If data is moved between different memories for processing, then heterogeneous devices can process data, but problems of high resource consumption and a high service processing delay are caused by the movement of the data between the different memories

Engineering Contradiction:
Improvedata processing capabilityVSAvoidresource consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent merges multiple separately configured memories into a unified shared memory pool that is accessible by all processor types (CPU, GPU, NPU, etc.). This consolidation eliminates redundant data copies and inter-memory data transfers, thereby reducing resource consumption while maintaining support for multiple computing power types.

Inventive Principle:
Principle #5Merging (Combining)

4Productivity

If data is moved between different memories for processing, then heterogeneous devices can process data, but a service processing delay is high

Engineering Contradiction:
Improvedata processing capabilityVSAvoidservice processing delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges multiple separately configured memories into a unified shared memory pool that is accessible by all processor types (CPU, GPU, NPU, etc.). This consolidation eliminates redundant data copies and inter-memory data transfers, thereby reducing resource consumption while maintaining support for multiple computing power types.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared memory pool enables continuous data processing by eliminating data transfer delays between separate memories. Data can be processed continuously across different processor types without interruption for memory copying, thereby reducing service processing delay.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12561247B2Device data processing using shared memory pool
Publication Date: 2026.02.24 HUAWEI CLOUD COMPUTING TECHNOLOGIES CO LTD
  • US12561247B2 patent drawing
  • US12561247B2 patent drawing
  • US12561247B2 patent drawing

AI summary

A computing device includes a central processing unit, at least one heterogeneous device, and a shared memory pool. The central processing unit is configured to: divide the shared memory pool into a plurality of memory spaces, store, in a first memory space in the plurality of memory spaces, first to-be-processed data that is provided by a client and that is associated with a service, and notify a first heterogeneous device of an address of the first to-be-processed data in the first memory space and a first operation that needs to be performed by the first heterogeneous device. The first heterogeneous device performs the first operation on the first to-be-processed data, and stores obtained first data in a second memory space.