Shared Memory Processor Array Latency Reduction
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Solution Overview
Problem
In parallel processing systems, particularly in SIMD data processors, the existing memory-multiplex architecture faces increased latency due to the need for pipelined memory access across multiple processing elements, which limits efficiency and increases memory requirements, compared to unpipelined structures with dedicated memory for each processor.
Innovation Solution
A data processor apparatus with a shared memory architecture where multiple data receiving units and computational elements operate at different speeds, allowing for differential timing of data transfer and processing, and sharing of resources like multipliers, SAD blocks, and ALUs, reduces latency and memory requirements while enabling deeper memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a memory time-multiplex CU architecture is used, then vertical data transfer between processing elements is efficient, but device latency is increased relative to unpipelined structures
Solution Approach 1:
The system divides processing into multiple pipelines, where each pipeline stage processes different data simultaneously. This segmentation allows overlapping of memory access and computation operations, reducing overall latency while maintaining efficient vertical data transfer through the interconnection network.
Solution Approach 2:
Data is pre-loaded into buffer memory before being processed by computational units. This preliminary action allows the system to overlap memory access time with computation time, reducing the critical path latency while maintaining high data transfer efficiency through the time-multiplexed architecture.
2Quantity of substance
If multiple CUs share the same memory space, then memory requirements per CU are reduced, but memory access must be pipelined increasing latency
Solution Approach 1:
A buffer memory structure is introduced as an intermediary between the shared memory space and multiple computational units. This buffer allows CUs to access data without direct contention on the main memory, enabling parallel access patterns that reduce latency while maintaining reduced memory requirements per CU through sharing.
Solution Approach 2:
The memory access architecture dynamically allocates access rights to different computational units based on operational needs. This dynamic approach allows the system to optimize memory bandwidth utilization and reduce access latency for shared memory resources while maintaining efficient memory sharing among multiple CUs.
3Use of energy by moving object
If data is downloaded from memory into CUs sequentially, then memory bandwidth is utilized efficiently, but processing throughput is reduced compared to parallel loading
Solution Approach 1:
The system maintains continuous useful action by overlapping data transfer and computation operations. While data is being transferred from memory to CUs through the interconnection network, computational units process previously transferred data, ensuring that both memory bandwidth and processing throughput are maximized simultaneously rather than sequentially.
Solution Approach 2:
The architecture introduces a temporal dimension to data transfer by implementing multi-stage buffering and pipelined transfer mechanisms. This allows data to be transferred across multiple dimensions (spatial through the interconnection network and temporal through pipelined stages), enabling efficient bandwidth utilization without sacrificing processing throughput.
Data Source
AI summary
A data processor apparatus comprises a plurality of data receiving means each for receiving data from a data source; a computational element coupleable to each of said data receiving means for performing an operation on said data; and a controller for controlling the flow of data from each data receiving means to the computational element.