Shared Memory Readout Circuit for OTP and MRAM
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Solution Overview
Problem
Existing memory circuits require individual sensing circuits for each bank of OTP and NVM cells, leading to increased space requirements and reduced consolidation of readout functions.
Innovation Solution
A memory circuit that includes a shared bit line coupled to both OTP and NVM cells, a configurable amplifier to generate an output voltage based on bit line signals, and an ADC to produce a digital output signal compared to stored threshold levels, thereby reducing space and increasing consolidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual sensing circuits are used for each bank of OTP and NVM cells, then measurement precision is improved, but device complexity and area increase
Solution Approach 1:
The patent merges the sensing circuitry into a shared infrastructure that serves both OTP and NVM cell banks. The amplifier and ADC are shared resources that can read from different cell types through multiplexed bit lines, eliminating the need for separate sensing circuits for each bank while maintaining readout accuracy through configurable read modes.
Solution Approach 2:
The sensing circuit is designed with multi-functionality to handle different cell types (OTP and NVM) through configurable operation modes. The amplifier can be configured to operate in different modes depending on whether it is reading from OTP or NVM cells, allowing a single universal sensing circuit to replace multiple dedicated circuits.
2Measurement precision
If individual sensing circuits are used for each bank of OTP and NVM cells, then measurement precision is improved, but area requirements increase
Solution Approach 1:
The patent merges the sensing circuitry into a shared infrastructure that serves both OTP and NVM cell banks. The amplifier and ADC are shared resources that can read from different cell types through multiplexed bit lines, eliminating the need for separate sensing circuits for each bank while maintaining readout accuracy through configurable read modes.
3Adaptability or versatility
If separate readout functions are used for OTP and NVM cells, then adaptability is improved, but device complexity increases
Solution Approach 1:
The sensing circuit is designed with multi-functionality to handle different cell types (OTP and NVM) through configurable operation modes. The amplifier can be configured to operate in different modes depending on whether it is reading from OTP or NVM cells, allowing a single universal sensing circuit to replace multiple dedicated circuits.
Solution Approach 2:
The readout circuit incorporates dynamic configurability where the amplifier and associated circuitry can switch between different operational modes based on the cell type being read. This dynamic adaptation allows the same hardware to serve multiple purposes without requiring separate static readout paths for each cell type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory circuit reduces space requirements and increases consolidation of readout functions while improving accuracy and yield by setting threshold levels based on measured memory cell parameters.
Implementation Method 1
a signal is generated having a value based on a path resistance of the NVM cell
Data Source
AI summary
A circuit includes a plurality of anti-fuse cells coupled to a first selection circuit, a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit, an amplifier including a first input terminal coupled to each of the first and second selection circuits, an analog-to-digital converter (ADC) including input terminals coupled to output terminals of the amplifier, and a comparator including a first input port coupled to an output port of the ADC. The amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to current levels received from the first selection circuit at the first input terminal of the amplifier and first voltage levels received from the second selection circuit at the first input terminal of the amplifier.