Shared Memory Refresh Masking for Multi-Processor Power Reduction
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Solution Overview
Problem
The one-chip architecture for mobile devices, which integrates an application processor and a connectivity processor into a single IC chip, is less efficient in terms of power consumption due to the need to manage the entire storage area of a common memory device even when only one of the chips is operating.
Innovation Solution
A common memory device is shared by at least two processors, with a memory cell array partitioned into separate regions for each processor, and a refresh masking information storage circuit and refresh circuit that selectively perform refresh operations based on masking information to optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a common memory device is shared by both processors in one-chip architecture, then the device size and configuration efficiency are reduced/improved, but power consumption optimization deteriorates
Solution Approach 1:
The memory device is divided into multiple independent memory regions (first memory region for first processor, second memory region for second processor). Each region can be independently managed and refreshed, allowing the system to refresh only the regions currently in use, thereby reducing overall power consumption while maintaining the space efficiency of shared memory architecture.
Solution Approach 2:
Instead of performing refresh operations on the entire memory device, the system performs partial refresh operations only on the specific memory regions that are currently allocated to active processors. This partial action approach reduces unnecessary power consumption while maintaining data integrity in the actively used memory portions.
2Use of energy by moving object
If selective refresh operations are implemented on memory regions, then power consumption is reduced, but device complexity increases
Solution Approach 1:
A memory management unit acts as an intermediary between the processors and the memory device. This intermediary component handles the complexity of region identification, allocation, and selective refresh control, thereby enabling power-efficient selective refresh operations without significantly increasing the complexity visible to the main processor systems.
Solution Approach 2:
The memory management unit performs multiple functions including memory region allocation, address mapping, and refresh control within a single integrated component. This multi-functionality approach consolidates the complexity into a dedicated management unit rather than分散 it across multiple components, achieving selective refresh capability without proportionally increasing overall device complexity.
Data Source
AI summary
A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first memory region allocated for the first processor and a second memory region allocated for the second processor, a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh is performed on at least one of the first and second memory regions, and a refresh circuit configured to selectively perform the refresh on the first memory region and the second memory region according to the refresh masking information.