Shared Memory Register Spilling to Cut GPU Data Access Latency

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Solution Overview

Problem

Conventional data spilling methods into external memory cause significant latency and pipeline bubbles, reducing program efficiency due to long data store/load paths.

Innovation Solution

A method and apparatus for spilling data into a shared memory, utilizing shared memory state and spill state information to calculate available address data, determining a target storage space, and storing virtual register data when the shared memory availability condition is met, thereby avoiding external memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is spilled into external memory, then sufficient storage capacity is ensured, but data access latency increases and pipeline efficiency decreases

Engineering Contradiction:
Improvestorage capacityVSAvoiddata access latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent introduces shared memory as an intermediary storage layer between registers and external memory. When register allocation is insufficient, data is spilled to shared memory instead of external memory. This intermediary approach provides sufficient storage capacity while maintaining faster access speeds, thereby reducing data access latency and avoiding pipeline bubbles.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If data is spilled into external memory, then storage capacity is sufficient, but program running efficiency decreases

Engineering Contradiction:
Improvestorage capacityVSAvoidprogram running efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

Shared memory serves as a mediator that enables sufficient data storage while maintaining high program running efficiency. By routing spill operations through shared memory rather than external memory, the system achieves both adequate storage capacity and fast access performance, eliminating pipeline stalls and improving overall productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If shared memory is used for data spilling, then data access speed improves, but shared memory availability constraints increase

Engineering Contradiction:
Improvedata access speedVSAvoidshared memory availability
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic shared memory management by calculating available address data based on current shared memory state and spill state information. The system adaptively determines target storage spaces by considering real-time memory capacity, occupancy, and data lifecycle. This dynamic approach allows the system to utilize shared memory efficiently for fast data access while adapting to changing availability constraints.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250355735A1Method and apparatus for spilling data into shared memory, computer device and storage medium
Publication Date: 2025.11.20 GLENFLY TECH CO LTD
  • US20250355735A1 patent drawing
  • US20250355735A1 patent drawing
  • US20250355735A1 patent drawing

AI summary

Disclosed are a method and apparatus for spilling data into a shared memory, a computer device, a computer-readable storage medium and a computer program product. The method includes: obtaining shared memory state information and spill state information of virtual register data to be spilled, the shared memory state information including memory address data and memory capacity data of at least one workgroup; calculating available address data according to the memory capacity data, the available address data representing a remaining capacity of the shared memory; calculating a virtual register spill amount according to the spill state information; calculating a target storage space according to the virtual register spill amount and the memory address data; determining a shared memory availability condition according to the available address data; and storing the virtual register data to be spilled into the target storage space when the target storage space meets the shared memory availability condition.