Shared Physical Memory Repair for Logical Address Conflicts
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Solution Overview
Problem
Existing memory built-in self-test (MBIST) controllers struggle to effectively repair logical memories due to conflicts arising from BISR parameters determined at a logical-memory level without considering underlying physical memory interrelationships, leading to potential memory errors and defective memory clusters.
Innovation Solution
Implement arbitration logic within each physical memory of a memory cluster to convert BISR parameters from logical-memory level to physical-memory level, ensuring proper operation of repair logic and preventing simultaneous activation of spare memory portions during conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MBIST controller tests multiple logical memories independently, then repair coverage is improved, but memory errors occur due to conflicting BISR parameters
Solution Approach 1:
The arbitration logic acts as an intermediary between the MBIST controller and the physical memory repair mechanisms. It receives BISR parameters from the MBIST controller and resolves conflicts by selecting appropriate spare memory portions, preventing simultaneous activation that would cause errors while maintaining comprehensive repair coverage across multiple logical memories.
Solution Approach 2:
The arbitration logic autonomously resolves conflicts between BISR parameters without requiring external intervention. It self-manages the selection of spare memory portions by monitoring conflicts and activating appropriate spares independently, ensuring reliable operation while maintaining full repair coverage.
2Reliability
If arbitration logic is added to resolve conflicts, then memory reliability is improved, but device complexity increases
Solution Approach 1:
The arbitration logic is segmented into modular conflict resolution units that can be integrated into existing memory structures. By dividing the arbitration function into discrete, manageable components rather than a monolithic complex system, the design achieves reliable conflict resolution while minimizing overall device complexity.
3Adaptability or versatility
If BISR parameters are determined at logical-memory level, then adaptability is improved, but manufacturing precision deteriorates due to physical memory conflicts
Solution Approach 1:
The arbitration logic serves as an intermediary layer between logical memory addressing and physical memory implementation. It translates logical-memory-level BISR parameters into precise physical memory addresses, resolving address mapping conflicts while preserving the independence and adaptability of logical memory organization.
Solution Approach 2:
The patent replaces complex mechanical address mapping mechanisms with logic-based arbitration. Instead of relying on precise physical alignment and manual configuration, the arbitration logic dynamically resolves address conflicts through logical operations, improving manufacturing precision while maintaining logical memory independence.
Data Source
AI summary
This document describes techniques, methods, and apparatuses for logical memory repair. In some aspects, a memory built-in self-test (MBIST) controller can perform logical memory repair for a memory cluster including a shared bus interface that is coupled to the MBIST controller and configured to provide access to multiple logical memories. The memory cluster includes multiple physical memories that are coupled to the shared bus interface. At least one physical memory is configured to have two or more logical memories overlaid thereon. In example aspects, the physical memory includes arbitration logic coupled to a first address register and a second address register that are respectively configured to store a first faulty memory address and a second faulty memory address. The arbitration logic includes circuitry configured to arbitrate access to at least one spare memory portion responsive to the first faulty memory address conflicting with the second faulty memory address.