Shared Memory Segment Overwrite Prevention via Dirty Bit Tracking
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Solution Overview
Problem
In advanced driver assistance systems (ADAS) and autonomous vehicles, shared memory between processing units is prone to overwriting due to the deletion of dirty bits during data transfers using different protocols, leading to data integrity issues.
Innovation Solution
Implementing an augmented hardware cache coherency protocol that maintains dirty bits information during data exchanges within a cache coherency domain, combined with an advanced extensible interface protocol for writing data to shared memory, ensures that only allocated segments are modified, preventing overwriting of other segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dirty bits are deleted during data transfers using different protocols, then data transfer efficiency is improved, but data integrity deteriorates due to overwriting of non-allocated segments
Solution Approach 1:
The patent introduces an intermediary mechanism (dirty bit management system) that mediates between data transfer operations and memory protection requirements. The system maintains dirty bit information as an intermediate state tracker, allowing efficient data transfers while preventing unauthorized overwrites by checking dirty bit status before allowing write operations to shared memory segments.
Solution Approach 2:
The patent implements a feedback mechanism where dirty bit status is continuously monitored and used to control subsequent write operations. When dirty bits indicate that a memory segment has been modified, the system provides feedback to prevent other processing units from overwriting those segments, thereby maintaining data integrity while allowing efficient transfers when appropriate.
2Adaptability or versatility
If shared memory is allocated to multiple processing units, then system versatility is improved, but risk of harmful overwriting increases
Solution Approach 1:
The patent divides shared memory into distinct allocatable segments and uses dirty bits to track the state of each segment. This segmentation allows multiple processing units to safely access different portions of shared memory simultaneously, improving versatility while preventing harmful overwrites through granular control at the segment level.
Solution Approach 2:
The patent applies different access permissions and protection levels to different segments of shared memory based on their allocation status and dirty bit values. Each memory segment has its own local quality characteristics (read-only, read-write, protected), allowing versatile memory sharing while preventing harmful operations in protected segments.
Data Source
AI summary
Techniques are disclosed for preventing overwriting of shared line segments. The techniques include sending a data unit from a first processor to second processor using an augmented hardware cache coherency protocol, the augmented hardware cache coherency protocol being augmented to maintain dirty bits information during an exchange of the data unit within a cache coherency domain. A size of the data unit is a fraction of a size of any shared line of a shared memory, and writing the data unit to a segment of a shared line of a shared memory includes using another protocol, without overwriting another segment of the shared line. The writing is based at least in part on the dirty bits information, and the other protocol does not support hardware coherency and maintains the dirty bits information.