Shared Memory Serialization Logic for Parallel Request Handling
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Solution Overview
Problem
Existing shared memory systems in multithreaded processor systems suffer from significant latency and overhead due to off-chip memory access and conflict resolution mechanisms, which hinder parallel processing efficiency.
Innovation Solution
A memory system where serialization logic selects one accessible location from multiple parallel requests, allowing all requests targeting that location to proceed while deferring and regenerating other requests, enabling low-latency access and parallel processing within a shared cache memory or directly accessed memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If shared memory is located on a separate chip from parallel processors, then memory capacity and accessibility are improved, but access speed and latency are worsened
Solution Approach 1:
The shared memory is divided into multiple banks, each capable of independent parallel access. This segmentation allows multiple processing elements to simultaneously access different banks without contention, thereby maintaining high access speed while providing broad memory accessibility across the parallel processor array.
Solution Approach 2:
The patent introduces a spatial dimension to memory access by organizing memory into multiple banks that can be accessed in parallel. This transforms the single-dimensional sequential access model into a multi-dimensional parallel access structure, enabling simultaneous access from multiple processing elements without sacrificing speed.
2Reliability
If semaphores or conflict resolution mechanisms are used to prevent conflicting access requests, then data consistency is improved, but processing overhead and latency are worsened
Solution Approach 1:
By dividing shared memory into multiple independent banks, the patent eliminates the need for semaphores and conflict resolution mechanisms. Each bank can be accessed independently by different processing elements simultaneously, ensuring data consistency through physical separation rather than software-based conflict management, thereby removing processing overhead associated with semaphore operations.
Solution Approach 2:
The patent extracts and removes the semaphore mechanism from the system by using hardware-based banked memory architecture that inherently prevents conflicts through physical separation of access paths. This eliminates the need for time-consuming semaphore acquisition and release operations while maintaining data consistency.
3Productivity
If multiple threads access the same memory location simultaneously, then parallel processing throughput is improved, but access conflict and data inconsistency are worsened
Solution Approach 1:
The shared memory is segmented into multiple banks, allowing multiple threads to simultaneously access different banks without conflict. This enables high parallel processing throughput while maintaining data consistency, as each bank operates independently with its own access path, eliminating the need for conflict resolution that would compromise either throughput or consistency.
4Speed
If cached copies of shared memory are maintained in each processor, then access speed is improved, but cache coherence overhead and memory usage are worsened
Solution Approach 1:
The patent extracts and eliminates the need for cached copies and cache coherence mechanisms by providing direct access to shared memory banks from multiple processing elements. This removes the complex cache coherence overhead while maintaining fast access speeds through the parallel banked memory architecture, achieving high-speed access without the complexity of distributed caching.
Data Source
AI summary
A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.