Shared Memory Interconnect with Snoop Filtering for Cache Coherency
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and outdated data, particularly when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, which includes coherent slave interfaces, an external memory master interface, and an arbiter circuit to manage memory access requests and determine snoop requests based on cache hit status and snoop filter state, ensuring coherent data access across processor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency monitoring system. The snoop filter bank and cache tag bank are hardware structures that automatically detect and manage cache coherency through hardware logic, eliminating the need for software intervention and thereby maintaining coherency without sacrificing operational efficiency.
Solution Approach 2:
The system implements self-service coherency management where the hardware structures (snoop filter bank, cache tag bank) automatically monitor and maintain cache coherency without external software control. The hardware autonomously detects coherency violations and initiates appropriate maintenance actions, freeing the software from managing coherency and improving overall system efficiency.
2Productivity
If hardware-based coherency management is implemented, then operational efficiency is improved, but device complexity increases due to additional hardware structures
Solution Approach 1:
The snoop filter bank and cache tag bank are designed to serve multiple functions within the memory controller. These structures not only monitor cache coherency but also participate in address translation and memory access management, thereby reducing the need for separate dedicated hardware components and mitigating the increase in device complexity.
Solution Approach 2:
The patent merges the coherency monitoring function with the existing memory controller structure by integrating the snoop filter bank and cache tag bank into the unified memory controller. This consolidation allows coherency management to be handled within the existing control logic framework, avoiding the need for entirely separate hardware subsystems and thereby limiting the increase in overall device complexity.
Data Source
AI summary
A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.