Shared On-Chip Memory for Flexible Network Analytics
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Solution Overview
Problem
Existing network switches lack flexibility in performing counting, traffic rate monitoring, and flow sampling due to dedicated memory usage and fixed processing units.
Innovation Solution
A centralized network analytic device with a shared pool of on-chip memory, where counting, monitoring, and sampling are defined through software, allowing for flexible configuration and efficient analytics across multiple pipeline stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated memory is used for each counter, rate monitor, and sampler, then reliability of analytics functions is improved, but device complexity and hardware resource usage increase
Solution Approach 1:
The patent merges previously separate dedicated memory resources for counters, rate monitors, and samplers into a single shared memory pool. This unified memory structure is accessed by multiple pipeline stages through a standardized interface, reducing overall device complexity while maintaining the reliability of each analytics function through proper memory management and access control.
Solution Approach 2:
The shared memory pool serves multiple analytics functions simultaneously - counters, rate monitors, and samplers all utilize the same memory resource. This universal memory structure eliminates the need for separate dedicated memories for each function, reducing hardware complexity while ensuring reliable operation of all analytics features through a common, well-managed memory interface.
2Manufacturing precision
If fixed processing units are used for counting, policing, and sampling, then manufacturing precision is improved, but adaptability to different analytics requirements deteriorates
Solution Approach 1:
The patent introduces dynamic configurability to previously fixed processing units. Pipeline stages can be dynamically assigned to different analytics functions (counting, policing, sampling) through software configuration rather than hardwired assignments. This dynamic allocation allows the system to adapt to varying analytics requirements while maintaining precise processing through the structured pipeline architecture.
Solution Approach 2:
The system enables parameter changes in processing unit functionality through software-controlled configuration. Pipeline stages can change their operational parameters and assigned functions based on traffic conditions and analytics requirements, transforming fixed processing units into adaptable resources that maintain manufacturing precision while gaining versatility.
3Measurement precision
If separate dedicated resources are allocated for each analytics function, then measurement precision is improved, but ease of operation and programming simplicity worsen
Solution Approach 1:
The shared memory pool provides a universal interface for all analytics functions, simplifying programming and operation. Instead of managing separate dedicated resources for each function, developers interact with a unified memory structure through standardized access patterns, reducing programming complexity while maintaining measurement precision through consistent memory access protocols.
Solution Approach 2:
The patent introduces an intermediary layer - the shared memory pool with standardized access interface - between the pipeline stages and the underlying memory resources. This intermediary simplifies operation by providing a uniform access mechanism for all analytics functions, eliminating the need for complex, function-specific memory management while preserving measurement accuracy through controlled access paths.
4Productivity
If on-chip memory is shared by all cores and pipeline stages, then hardware resource efficiency is improved, but access conflict and processing time may increase
Solution Approach 1:
The shared memory pool is segmented into multiple banks or regions that can be accessed by different pipeline stages simultaneously. This segmentation allows parallel access to different memory portions, reducing access conflicts and timing delays while maintaining high resource efficiency. Multiple cores and pipeline stages can operate concurrently on different memory segments without significant interference.
Data Source
AI summary
Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.