Shared Memory Crossbar Switch Fabric with Dynamic Path Selection
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Solution Overview
Problem
Current computer network routers face challenges in efficiently managing high volumes of network traffic, particularly in handling congestion within switch fabrics, which can lead to increased latency and reduced performance.
Innovation Solution
The implementation of a shared memory crossbar switch with a low latency path that bypasses shared memory when output queues reach a certain threshold, allowing for dynamic switching between low latency and shared memory paths based on queue occupancy, thereby optimizing cell transfer and reducing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cells are transferred through shared memory to handle congestion, then network capacity and reliability are improved, but latency increases
Solution Approach 1:
The system dynamically switches between two transfer paths (shared memory path and low latency path) based on real-time queue occupancy conditions. When output queue occupancy is below a threshold, the low latency path is used; when the threshold is exceeded, the shared memory path is activated. This dynamic adaptation resolves the contradiction by selecting the appropriate path for current network conditions.
Solution Approach 2:
The shared memory acts as an intermediary storage mechanism that cells can route through when congestion is detected. The crossbar switch serves as another intermediary component that can route cells through different paths. These intermediaries enable flexible routing decisions that balance latency and reliability requirements.
2Productivity
If a shared memory crossbar switch is used to handle high traffic volumes, then network throughput is improved, but device complexity increases
Solution Approach 1:
The switch fabric is segmented into multiple independent crossbar switches, each handling specific input-output port combinations. This segmentation allows parallel processing of multiple cell streams simultaneously, increasing overall throughput while keeping each individual crossbar switch relatively simple in structure.
Solution Approach 2:
The shared memory component serves multiple functions: it acts as temporary storage for congested cells, provides flow control mechanisms, and enables dynamic path selection. This multi-functionality reduces the need for separate dedicated components, thereby managing device complexity while maintaining high throughput capability.
3Loss of time
If output queues are monitored and dynamic path switching is implemented, then latency is reduced during normal operation, but control complexity increases
Solution Approach 1:
The system continuously monitors output queue occupancy and uses this feedback information to make real-time routing decisions. When queue occupancy exceeds a predefined threshold, the feedback triggers switching to the shared memory path; when the threshold is cleared, it triggers switching back to the low latency path. This feedback mechanism automates the control process, reducing the need for complex manual control logic.
Solution Approach 2:
The system changes the routing parameter (transfer path selection) based on the parameter change in queue occupancy. This parameter-based control simplifies the decision-making process by using a clear threshold criterion rather than complex algorithms, thereby reducing control complexity while still achieving low latency performance.
Data Source
AI summary
A system and method of transferring cells through a switch fabric having a shared memory crossbar switch, a plurality of cell receive blocks and a plurality of cell transmit blocks. The system determines, based on a number of cells queued up in respective output buffers in the cell transmit blocks, output buffers in the cell transmit blocks that can receive cells on a low latency path. The cells transferred include first cells that can be transferred on the low latency path and second cells that cannot be transferred via the low latency path. The first cells are transferred via a bypass mechanism in shared memory to the output buffers. The second cells are transferred by writing the second cells to shared memory, reading the second cells from shared memory and transferring the second cells read from shared memory to the output buffers in the cell transmit blocks.