Shared Memory Switch for FPGA Protocol Adaptability
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Solution Overview
Problem
Traditional network switches, especially those using ASICs, are limited in supporting various communication protocols and require significant logic resources, making them inflexible and inefficient in terms of memory usage, particularly when handling different data protocols on Field Programmable Gate Arrays (FPGAs).
Innovation Solution
A protocol-agnostic cell-based switch using BlockRAM memory on FPGAs, which implements a scalable memory architecture with pipelining and data pointers to manage data storage and retrieval efficiently, reducing memory and logic resource usage by eliminating the need for addressing and link lists, and allowing customizable port data-paths and scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional ASIC-based network switches are used to support specific protocols, then protocol-specific performance is optimized, but adaptability to different communication protocols is lost
Solution Approach 1:
The patent implements a universal memory-based switching architecture that can handle multiple communication protocols (Ethernet, InfiniBand, PCI Express, etc.) through a single unified structure. The memory switch uses a common memory array and control logic that adapts to different protocols without requiring separate dedicated switching fabrics for each protocol type.
Solution Approach 2:
The switching architecture employs dynamic resource allocation where memory bandwidth and access patterns are adjusted based on the active protocol and traffic demands. The system can dynamically reconfigure memory access modes, arbitration schemes, and data path widths to optimize performance for the currently active communication protocol.
2Adaptability or versatility
If memory-based switching with buffering is implemented to support packet data formats, then protocol support is improved, but logic resource consumption on FPGA increases significantly
Solution Approach 1:
The patent extracts the switching function from complex protocol-specific logic and relocates it to a simplified memory-based architecture. By removing protocol-specific switching logic and replacing it with universal memory access control, the design significantly reduces FPGA logic resource consumption while maintaining multi-protocol support capabilities.
Solution Approach 2:
Instead of implementing multiple parallel switching paths for different protocols, the patent uses a single shared memory structure that serves all protocols. The same physical memory resources are copied and accessed by different protocol handlers, eliminating the need for duplicate logic structures for each protocol.
3Speed
If crossbar switch architecture is used for direct node interconnection, then latency is minimized, but support for packet/cell data formats is lost
Solution Approach 1:
The patent merges the low-latency direct connection advantage of crossbar switches with the packet buffering capability of memory structures. The architecture combines fast memory access paths with traditional crossbar switching, allowing packets to be buffered in memory while maintaining high-speed transfer capabilities through optimized memory-to-memory direct paths.
Data Source
AI summary
A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.