On-Chip Shared Memory Switch for RAID-on-a-Chip Scalability
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Solution Overview
Problem
Current RAID on a Chip (ROC) architectures face limitations in scaling performance due to lack of multi-processor support, fabric contention, bus contention, and reliance on off-chip memory, leading to bottlenecks in CPU processing speed, data movement efficiency, and DMA management complexity.
Innovation Solution
A novel system-on-a-chip architecture featuring a global shared memory switch (GSM) with on-chip shared memory resources, prioritized low-latency paths, and unified addressing schemes to enable concurrent access and processing across multiple processors and hardware engines, minimizing off-chip memory access and optimizing DMA operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single CPU is used in traditional ROC architecture, then device complexity is reduced, but CPU processing speed becomes a bottleneck limiting system performance
Solution Approach 1:
The system is divided into multiple independent processor complexes, each capable of autonomous operation. Each processor complex includes its own CPU, instruction cache, and access to shared memory resources, allowing parallel processing of RAID operations and eliminating the single CPU bottleneck while maintaining manageable complexity through modular design
Solution Approach 2:
The shared memory resources and interconnect fabric are designed to be universally accessible by all processor complexes and hardware engines. The same memory structures serve multiple functions: caching data for different processors, storing DMA buffers, and providing shared workspace for various hardware engines, thereby supporting multi-processor operation without proportionally increasing overall system complexity
2Loss of time
If off-chip memory is used for data storage, then memory capacity is increased, but access latency and power consumption increase
Solution Approach 1:
Multiple levels of memory caching are implemented in a hierarchical structure. L1 and L2 data caches are nested within each processor complex for fast local access, while additional shared memory structures provide extended caching capacity. This nested approach provides frequently accessed data close to the processors, dramatically reducing access latency compared to off-chip memory while utilizing on-chip memory resources efficiently
Solution Approach 2:
Data is pre-loaded into on-chip cache memory structures before being needed by the processors. The system anticipates data access patterns and maintains relevant data in fast on-chip memory, eliminating the need for frequent off-chip memory accesses and thereby reducing both latency and power consumption during actual processing operations
3Productivity
If fabric contention is eliminated through dedicated paths, then data movement efficiency is improved, but device complexity increases
Solution Approach 1:
Different interconnect paths are optimized for different types of traffic based on local requirements. Critical time-sensitive communications between processor complexes use low-latency direct paths, while less time-critical data transfers use the shared fabric. This localized optimization of path characteristics improves overall data movement efficiency without requiring complete dedication of all paths, thereby controlling complexity
4Ease of operation
If DMA operations are simplified, then ease of operation is improved, but DMA management complexity increases
Solution Approach 1:
The DMA engine is designed with automatic buffer management capabilities. It autonomously allocates and manages DMA buffers in shared memory, performs address translation, and handles data transfer operations without requiring complex software intervention. This self-service approach simplifies the interface for software while the underlying DMA management complexity is handled automatically by the hardware engine itself
Data Source
AI summary
A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.