Shared Memory Switching for Transmission Path Delay Adjustment

The patent merges the delay adjustment function into a single shared memory unit that serves both 0-system and 1-system transmission paths. Instead of having separate large-capacity memories for each path, one memory is used to buffer signals from either path, achieving the same uninterrupted switching capability with reduced total memory capacity.

The single memory unit is designed to perform multiple functions: it can buffer signals from the 0-system path, buffer signals from the 1-system path, and provide delay adjustment for either path as needed. This multi-functional design eliminates the need for dedicated large-capacity memories for each transmission path.

The patent implements dynamic memory allocation where a single memory unit is flexibly assigned to buffer signals from either the 0-system or 1-system path based on real-time switching requirements. The memory connection control unit dynamically connects the memory to the appropriate path, allowing precise delay adjustment without requiring simultaneous large-capacity memory for both paths.

The single memory unit is pre-configured with sufficient capacity to handle the maximum required delay adjustment for either transmission path individually. By preparing the memory in advance with adequate capacity and using it alternately for different paths, the system achieves precise delay adjustment without needing doubled memory capacity.