Shared Memory TDM Banking to Cut Crossbar Complexity
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Solution Overview
Problem
Multiported memories in multicore processor environments face challenges of increased complexity, cost, and power consumption due to the exponential growth of routing and control logic with the number of ports and memory addresses, necessitating sophisticated arbitration mechanisms that complicate design and fabrication.
Innovation Solution
Implementing a time division multiplexing shared memory system that divides ports into sets for cyclic access to memory banks, using lane access and data swizzling to reduce routing and arbitration complexity, and employing selection circuits and cross bar circuits to manage access requests efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of ports and memory addresses in a multiported memory increases, then the parallel access capability and throughput are improved, but the routing and control logic complexity grows exponentially
Solution Approach 1:
The patent segments the memory system into multiple memory banks (e.g., 8 banks) that can be independently accessed. Each bank is assigned to specific ports through time-division multiplexing, dividing the overall routing complexity into smaller, manageable segments rather than requiring a complete crossbar for all ports simultaneously.
Solution Approach 2:
The patent implements periodic time-division multiplexing where ports are granted access to memory banks in cyclic periods. Each port receives periodic access to different banks in a round-robin fashion, eliminating the need for complex simultaneous routing by using time-based multiplexing instead of space-based routing for all connections.
2Productivity
If the number of ports and memory addresses increases, then the parallel access capability is improved, but the hardware resources and power consumption increase
Solution Approach 1:
By segmenting the memory into multiple banks and assigning them to specific ports through time-division multiplexing, the patent reduces the active hardware resources needed at any given time. Only the selected bank and its associated routing paths are active, rather than requiring all routing paths to be simultaneously active, thereby reducing power consumption.
Solution Approach 2:
The periodic time-division multiplexing scheme ensures that routing and control logic are activated only when needed for the currently serving port-bank pair, rather than remaining continuously active. This periodic activation significantly reduces average power consumption while maintaining full parallel access capability when multiple ports are served in sequence.
3Productivity
If the number of ports and memory addresses increases, then the parallel access capability is improved, but the design and fabrication difficulty increases
Solution Approach 1:
The patent divides the memory system into modular memory banks that can be independently designed and fabricated. Each bank has a standardized interface and control logic, allowing for modular design that simplifies fabrication compared to a monolithic approach. The time-division multiplexing architecture also reduces the complexity of interconnect routing between ports and banks.
Solution Approach 2:
The periodic time-division multiplexing architecture simplifies the routing design by using time-based addressing rather than requiring complex spatial routing for all port-bank connections simultaneously. This reduces the number of routing traces and control signals needed, making the design easier to implement and fabricate while maintaining high parallel access capability.
4Productivity
If the number of ports and memory addresses increases, then the parallel access capability is improved, but the arbitration complexity increases
Solution Approach 1:
The patent segments the arbitration process into bank-level arbitration units, each responsible for managing access to its assigned memory bank. This divides the overall arbitration complexity into smaller, independent units that operate in parallel, reducing the complexity of any single arbitration decision while maintaining system-wide coordination through the time-division multiplexing schedule.
Solution Approach 2:
The periodic time-division multiplexing schedule provides a predetermined access pattern that simplifies arbitration. Instead of requiring complex real-time arbitration for all ports simultaneously, the system uses periodic round-robin scheduling where each port has a predetermined turn to access specific banks, significantly reducing arbitration logic complexity while maintaining fair and efficient access.
Data Source
AI summary
Systems and methods related to time division multiplexing shared memories are disclosed herein. A shared memory system may use time division access techniques, lane access techniques, or both to reduce the complexity of cross bar circuits while maintaining high throughput. The memory system may comprise a set of port groups, a set of selection circuits coupled to the set of port groups in a one-to-one correspondence, a set of memory banks, and a time division multiplexing control system. The time division multiplexing control system may be coupled to a set of control inputs of the set of selection circuits, and may be configured to couple, in a cycle of one-to-one correspondences, the set of port groups to the set of memory banks. The memory system may divide memory banks and client ports into separate lanes based on address bits, where each lane operates independently with dedicated routing circuits.