Shared Memory Computing Architecture with Timeslot Interconnect
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Solution Overview
Problem
Shared memory computing devices with multiple bus-masters experience real-time issues due to unwanted timing interference from unrelated memory transfer requests, leading to significant delays in servicing memory transfer requests over shared interconnects like ARM AMBA AHB.
Innovation Solution
A shared memory computing architecture with multiple interconnect masters and targets, utilizing a timeslot-based interconnect that decouples memory transfer requests and responses, allowing each interconnect master to issue requests independently without interference, and employing cache modules with update-type cache coherency policies to maintain timing integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple bus masters share a common interconnect for memory transfers, then device complexity is reduced and resources are shared, but timing interference occurs causing unpredictable worst-case execution times
Solution Approach 1:
The interconnect is segmented into multiple independent timeslots, with each timeslot dedicated to a specific interconnect master. This segmentation eliminates timing interference between masters while maintaining resource sharing, as each master operates in its assigned timeslot without contention from others.
Solution Approach 2:
The interconnect operates using periodic timeslots that are cyclically assigned to different interconnect masters. This periodic structure ensures that each master receives guaranteed access to the interconnect at regular intervals, providing predictable worst-case execution times while maintaining efficient resource utilization through cyclic rotation.
2Productivity
If memory transfer requests are serviced over a shared interconnect, then resource utilization is improved, but unrelated memory transfer requests cause timing interference and delays
Solution Approach 1:
The shared interconnect is divided into separate timeslots for different masters, segmenting the resource access in time. This allows high resource utilization through sharing while ensuring timing predictability, as each master has guaranteed access during its assigned timeslot without interference from unrelated requests.
Solution Approach 2:
Timeslots are pre-allocated to interconnect masters in advance, establishing a predetermined schedule for resource access. This preliminary assignment ensures that each master knows when it will gain access to the interconnect, providing timing predictability while maintaining efficient resource utilization through the pre-planned sharing arrangement.
3Device complexity
If a single interconnect services multiple masters, then device complexity is minimized, but a single request can block the bus for multiple clock cycles
Solution Approach 1:
The interconnect is segmented into multiple timeslots that can operate in parallel for different masters. This segmentation allows the system to maintain a simple single-bus structure while achieving higher effective throughput, as multiple transfers can be initiated in different timeslots without one blocking the others.
Solution Approach 2:
The timeslot-based interconnect maintains continuous useful action by ensuring that while one master is transferring data, other masters can simultaneously initiate or complete transfers in their assigned timeslots. This eliminates idle bus periods and maintains continuous productive activity, improving overall throughput without increasing structural complexity.
Data Source
AI summary
A shared memory computing device optimised for executing realtime software that has at least one interconnect master, a shared memory, N cache modules and M processor cores, where the value of N>=1 and M =N. Each of the N cache modules has a means to implement an update-type cache coherency policy across those N cache modules. Each processor core is assigned a different one of the N cache modules as that processor core's private cache. Furthermore, the memory transfer request latency of non-atomic memory transfer requests issued by each of the M processor cores to the shared memory is not modified by: (a) the memory transfer requests issued by any of the other M processor cores; or (b) the memory transfer requests issued by at least one other interconnect master.