Shared Memory Pixel Layout for Small-Footprint ToF Sensing
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Solution Overview
Problem
Time-of-flight (ToF) systems face challenges in efficiently laying out shared memory bins for distance calculation due to layout constraints, particularly in sub-10µm pitch and full-well depth requirements, affecting cost, resolution, power consumption, and module z-height in 3D SPAD imagers.
Innovation Solution
Implementing a shared Static Random Access Memory (SRAM) among multiple pixels, utilizing a time-multiplexed arithmetic logic unit (ALU) to reduce layout space and power consumption, allowing for smaller footprint and higher photon capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a register file is used to store pixel data in a pixel circuit, then random access to pixel data is enabled, but the circuit area increases significantly
Solution Approach 1:
The patent extracts the random access functionality from the pixel circuit itself by removing the register file and implementing access control through shared memory banks with address decoding logic. This separates the storage function (in external memory) from the access control function (in the pixel circuit), thereby reducing in-pixel circuit area while maintaining random access capability through software-controlled memory addressing.
Solution Approach 2:
The patent implements multi-functional pixel circuits that can operate in different modes (read, write, update) without requiring dedicated hardware for each function. The same pixel circuit infrastructure supports multiple operations by dynamically configuring memory bank access patterns, eliminating the need for separate register files for different access modes and reducing overall circuit complexity.
2Area of stationary object
If pixel circuits are simplified by removing register files, then circuit area is reduced, but control over data access becomes more complex
Solution Approach 1:
The patent introduces an intermediary address decoding mechanism that translates logical pixel addresses into physical memory bank addresses. This intermediary layer manages the complexity of access control by providing a systematic addressing scheme that simplifies the interface between pixel circuits and shared memory, making the system easier to control despite the removal of register files.
Solution Approach 2:
The patent replaces the mechanical/hardware-based register file access control with a software-based memory management system. Instead of hardwired control logic for each pixel, the system uses programmable memory addressing and bank selection, allowing flexible access patterns to be controlled through software rather than complex hardware logic.
3Area of stationary object
If multiple pixel circuits share the same memory bank, then circuit area is reduced, but access conflicts increase
Solution Approach 1:
The patent segments the shared memory into multiple independently addressable memory banks, where each pixel circuit is associated with specific memory banks. This segmentation allows parallel access to different memory banks by multiple pixel circuits simultaneously, reducing access conflicts while maintaining area efficiency through shared memory resources.
Solution Approach 2:
The patent introduces an additional dimension of organization by implementing a two-dimensional memory addressing scheme with bank selection and byte offset components. This dimensional organization allows multiple pixel circuits to access different portions of the same physical memory simultaneously without conflict, effectively multiplying the available access paths and reducing contention.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A Time of Flight (TOF) system includes an incrementing circuit and a plurality of pixels. Each pixel includes a plurality of detectors configured to output respective detection signals responsive to detection of a plurality of photons incident thereon and a shared memory configured to store a respective count of the photons incident on each of the plurality of detectors. The incrementing circuit is configured to update the respective count for each of the plurality of detectors in the shared memory based on the respective detection signals.