Vehicle Signal Processing with Shared Memory for Low-Latency IPC
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Solution Overview
Problem
Existing vehicle network gateways face challenges in achieving high-speed and real-time data transmission due to low bandwidth and unnecessary memory copy, leading to latency and memory overhead during inter-processor communication.
Innovation Solution
A signal processing device with a first and second processor, each handling different communication schemes, and a shared memory for inter-processor communication, along with cache management and priority queuing to minimize latency and buffer occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional communication protocols (UART, SPI) are used for inter-processor communication, then device compatibility and ease of implementation are improved, but data transmission speed and bandwidth are reduced
Solution Approach 1:
The patent replaces traditional mechanical/electrical communication protocols (UART, SPI) with a shared memory-based communication mechanism. Processors directly access each other's memory spaces through defined address ranges, eliminating the need for physical communication buses and protocol handshaking. This substitution enables significantly higher data transmission speeds while maintaining implementation simplicity through standardized memory-mapped I/O operations.
2Reliability
If traditional communication protocols with separate memory buffers are used, then data transmission reliability is improved, but memory overhead and latency are increased
Solution Approach 1:
The patent merges the communication channel and data storage into a unified shared memory structure. Instead of using separate transmission buffers and storage memory, the same memory space serves both purposes. This elimination of redundant memory copies and intermediate buffers reduces latency while maintaining data reliability through memory protection mechanisms and atomic operations.
Solution Approach 2:
The patent eliminates unnecessary data copying between separate buffers by implementing direct memory access between processors. Data is written once to the shared memory and read directly by the receiving processor, avoiding multiple copy operations that increase latency. Memory protection bits ensure data integrity without requiring additional copying for verification.
3Adaptability or versatility
If multiple copies of the same data are stored in separate buffers, then data availability for multiple processors is improved, but buffer occupancy and memory usage are increased
Solution Approach 1:
The shared memory space serves multiple functions simultaneously: it acts as both the communication channel and the data storage for multiple processors. The same memory region can be accessed by different processors for different purposes depending on the address being accessed, eliminating the need for duplicate buffers. Memory protection registers control which processors can access which memory regions, providing versatile data availability without increasing memory usage.
Data Source
AI summary
A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.