Shared-Memory Inter-Processor Signaling for Low-Latency Vehicle Communication
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Solution Overview
Problem
Existing vehicle communication devices face challenges in achieving low latency and high-speed data transmission due to limitations in communication protocols like UART and SPI, which result in inefficient data transmission and increased latency, especially during inter-processor communication.
Innovation Solution
A signal processing device with a first processor configured to receive messages based on a first communication scheme, a second processor configured to receive messages based on a second communication scheme, and a shared memory for transmitting messages between processors, utilizing an interrupt router and dynamic bandwidth adjustment to optimize data transmission without a locking mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If communication protocols like UART and SPI are used for inter-processor communication, then device compatibility and ease of implementation are improved, but data transmission speed and latency performance deteriorate
Solution Approach 1:
The patent introduces a shared memory as an intermediary component between processors, replacing direct protocol-based communication (UART/SPI) with memory-based data exchange. This mediator enables high-speed data transfer by eliminating protocol overhead and unnecessary memory copy operations, while processors can access the shared memory directly through memory interfaces rather than serial protocols.
Solution Approach 2:
The patent replaces mechanical/physical communication protocols (UART/SPI hardware interfaces with serial transmission) with an electronic memory-based system. By substituting the serial communication mechanism with parallel memory access, the system achieves significantly higher transmission speeds and lower latency while maintaining implementation feasibility through standard memory interfaces.
2Adaptability or versatility
If traditional communication protocols with memory copy operations are used, then system compatibility is improved, but latency and real-time performance deteriorate
Solution Approach 1:
The patent extracts and removes the unnecessary memory copy operation from the communication path. By having processors access the shared memory directly without intermediate copying, the system eliminates a significant source of latency while maintaining compatibility through standardized memory interfaces. The shared memory acts as a direct communication channel rather than a buffer requiring data duplication.
3Reliability
If processors use locking mechanisms for memory access, then data consistency is improved, but processing speed and real-time response deteriorate
Solution Approach 1:
The patent segments the shared memory into distinct regions or channels that can be accessed by different processors simultaneously without conflict. By dividing the memory space into independent access zones, the system eliminates the need for global locking mechanisms while maintaining data consistency within each segment. Processors can operate in parallel on different memory segments without mutual exclusion overhead.
4Productivity
If dynamic bandwidth adjustment is implemented, then data transmission efficiency is improved, but system complexity increases
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by allowing processors to access different portions of the shared memory with varying access widths and speeds based on real-time communication needs. The memory interface can dynamically allocate bandwidth to different processors or data streams, optimizing transmission efficiency for different message sizes and priorities without requiring complex reconfiguration of the underlying hardware architecture.
Data Source
AI summary
A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor to receive a first message including a sensor signal based on a first communication scheme and to process the received first message; a second processor to receive a second message including a communication message based on a second communication scheme and to process the received second message; and a shared memory to operate to transmit the first message or the second message between the first processor and the second processor, wherein the first processor or the second processor is configured to receive the first message or the second message stored in the shared memory based on an interrupt signal. Accordingly, latency may be reduced and high-speed data transmission may be performed during inter-processor communication.